Forum: FPGA, VHDL & Verilog Single Entity - Multiple architectures

Author: SM (Guest)
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I am a beginner in VHDL, I have a very basic question regarding Single 
Entity having multiple architectures. For example when the VHDL code is 
compiled (a single file containing one entity and 3 architectures), how 
does the compiler will decide which is the default architecture; or 
there isn't anything like Default Architecture.

I will be really grateful to any help from experts here.
Thanks in advance.

Author: cfgardiner (Guest)
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In the VHDL standard this is defined in the chapter on "default Binding 
Indication". VHDL differentiates between Primary design units (Entity, 
Package Header, Configuration) and Secondary design units (architecture 
body, package body).

You must compile (well, analyse in the VHDL terminology) a primary 
design unit first. Sort of logical if you think about it, except perhaps 
for configurations. Configurations only become 'real' at elaboration 
time, i.e. after you have analysed everything into a library and are 
building your model, starting your simulation or whatever.

If you compile multiple secondary units and don't specify a binding 
(e.g. link a specific architecture to a specific entity) then the 
default binding is the "most recently analysed" architecture .... the 
last one analysed.


: Edited by Moderator


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