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Forum: FPGA, VHDL & Verilog Not synthesizing


Author: Vinayak S. (vinayak_s)
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Hi.....

I used signal(0 to 64800)integer in VHDL and which is not 
synthesizing....
Insted of using signal/variable is there any method we can use for large 
values.... ?

Ex:

Buf1(64799 downto 0);--integers
Buf1(64799 downto 0);

Author: Innensechskant (Guest)
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I can't see any problem with the declaration shown.

Please post complete and minimal code which shows the problem along with 
the error message(s). In case of VHDL this consists an entity and an 
appropriate testbench.

Author: Vinayak S. (vinayak_s)
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Here I used temp0 as signal which is not synthesizing....Which code as 
shown below help me out in this issue....

modelsim 6.5 working fine but for xilinx 10.3 which is not 
synthesing.....
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.signed;

entity parity_int is 
  port( clk : in std_logic;
        reset: in std_logic;
        nm_sh_sel:in std_logic;
        code_rate:in std_logic_vector(3 downto 0);
        K_ldpc: in std_logic_vector(15 downto 0);
        N_ldpc:in std_logic_vector(15 downto 0);
        input1: in std_logic;
        output1: out std_logic);
         
  end parity_int;
   
  architecture arch of parity_int is  
  --Both normal and short are in one array. if we select normal then it gives 0 to 9 and 
  -- if we select the short then code_rate plus 6 need to add.
  type Q_ldpc_normal is array (0 to 14) of integer;
  constant Q_ldpc:Q_ldpc_normal:=(90,72,60,45,36,30,36,30,27,25,18,15,12,10,8);
  
  signal count1:integer;
  signal s:integer;
  signal t:integer;
  signal temp0:std_logic_vector(0 to 64799);
  signal cd_rate:std_logic_vector(3 downto 0);
  
  begin
  cd_rate <= code_rate when nm_sh_sel = '0' else code_rate + 6 ;  
    
    process(clk,reset)
       begin
         if((clk'event and clk = '1') or reset = '1') then
           if reset = '1' then
             count1 <= 0;
           else
             if count1 = to_integer(unsigned(N_ldpc))+to_integer(unsigned(K_ldpc)) + 1 then --32400+64800
               count1 <= 0;
             else
             count1 <= count1 + 1;
           end if;
         end if;
       end if;
     end process;
     
      process(count1,t)
       begin
         
           if reset = '1' then
             s <= 0;
           else
             
             if count1 >= to_integer(unsigned(K_ldpc)) + 1 and count1<to_integer(unsigned(N_ldpc)) +1 then 
            
             if s = 360 then
                s <= 0;
               
             else
                
                s <= s + 1;
           
           end if;
         end if;
       end if;
     end process;
     
      process(count1)
       begin
        
           if reset = '1' then
             t <= 0;
           else
             if count1 >= to_integer(unsigned(K_ldpc)) + 1 and count1 < to_integer(unsigned(N_ldpc)) + 1 then              
             if t = Q_ldpc(to_integer(unsigned(cd_rate)))   then
                t <= 0;
               
             else
               
               if s = 360 then
                t <= t + 1;
              end if;
           end if;
         end if;
       end if;
     end process;
     
     process(count1,reset)
       begin
         if count1 >= 1 and  count1 < to_integer(unsigned(K_ldpc)) + 1  then
         temp0(count1 - 1) <= input1; -- it took one extra cycle because input delay by one cycle... 
         
       elsif count1 >= to_integer(unsigned(K_ldpc)) + 1 and count1 < to_integer(unsigned(N_ldpc)) + 1 and t < 90 then
         temp0(to_integer(unsigned(K_ldpc)) + (360 * t) + s ) <= input1;
         output1 <= temp0(count1 - to_integer(unsigned(K_ldpc)) - 1);----32401-32400-1=0
         
       elsif count1 >= to_integer(unsigned(N_ldpc)) + 1 and count1 < (to_integer(unsigned(N_ldpc)) + to_integer(unsigned(K_ldpc)) + 1) then
         output1 <= temp0(count1 - to_integer(unsigned(K_ldpc)) - 1);
         
       end if;
  
end process;
end arch;

: Edited by Moderator
Author: Innensechskant (Guest)
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The file extension for VHDL files is "vhd".
Please use tags as mentioned in the "formatting" section.

It is most likely that you got some warnings and errors.
At least because:
  signal temp0:std_logic_vector(0 to 64799);

does not declare an integer in the range from 0 to 64799 but a
standard logic vector (i.e. a bit vector) with indixes 0 to 64799 
instead which is far to large, to broad, to be synthesized.

Author: Innensechskant (Guest)
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I'm sorry: It must be: "... which is far too large, too broad, to be 
synthesized."

Author: Lothar Miller (lkmiller) (Moderator)
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Vinayak S. wrote:
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
> use ieee.numeric_std.signed;
You really don't know what you are doing? Just digging around?
Take these two:
  use ieee.std_logic_1164.all;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
Or those:
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.signed;
Or (much better) this one:
  use ieee.numeric_std.all;
But never ever use all of them together!!

This forms a combinatorial loop:
      process(count1,t)
       begin
         
           if reset = '1' then
             s <= 0;
           else
              :
              s <= s + 1;
You just don't see it in simulation because the sensitivity list is 
incomplete: s is missing...  :-/
Same for t in the following:
      process(count1)
       begin
        
           if reset = '1' then
             t <= 0;
           else
              :
                t <= t + 1;

And what the heck is this:
    process(clk,reset)
       begin
         if((clk'event and clk = '1') or reset = '1') then
           if reset = '1' then
             count1 <= 0;
           else
             if count1 = 
               count1 <= 0;
             else
               count1 <= count1 + 1; 
A kind of asynchronous reset hidden in the clocked part of a process? 
Where did you find this way of VHDL coding?

Vinayak S. wrote:
> modelsim 6.5 working fine but ...
... your simulation is wrong because of the mostly incomplete 
sensitivity lists.

: Edited by Moderator
Author: Innensechskant (Guest)
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No worth in mentioning all the other ... hmm ... peculiarities.
An attempt to write a DVB-T decoder 
(http://embdev.net/topic/322606#3509435) which on the other hand does 
not know basic datatypes... Waste of time.

Author: Vinayak S. (vinayak_s)
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Thank you for valuable reply....
 process(clk,reset)    ---- counter
    begin
      if reset='1' then
        count1 <= 0;
      
      elsif rising_edge(clk) then
        count1 <= 0;

        if count1 =64800 then 
          count1 <= 0;
        else
          count1 <= count1 + 1;
        end if;
      end if;    
  end process;

I modified counter program like that "THIS WAY IS GOOD"....?

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
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Vinayak S. wrote:
> I modified counter program like that "THIS WAY IS GOOD"....?
Yes, because thats the usual way to describe a counter.
Apart from the asynchronous reset and the fact that one line isn't 
necessary:
   :
   elsif rising_edge(clk) then
      count1 <= 0;    -- not useful and not necessary
      if count1 =64800 then 
         count1 <= 0;
      else
      :

Author: Vinayak S. (vinayak_s)
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Thank you for correcting......

I stack in designing pls help me.....

What is the solution for large values like 64800*8 interger values need 
to store in register/buffer before using this reg/buf.
Means to say I have store large values of Address and utilize them in 
program.

Author: Falk (Guest)
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@Vinayak S. (vinayak_s)

>I stack in designing pls help me.....

No, you are lacking basic knowledge of VHDL and digital design.
VHDL ist NOT just another programming language!
It is, as the name implies, a hardware description language.

>What is the solution for large values like 64800*8 interger values need
>to store in register/buffer before using this reg/buf.

A RAM. Available in any decent FPGA.

>Means to say I have store large values of Address and utilize them in
>program.

Just do it. After you did your homework and got a grip of the basics. 
Otherwise, forget it.

Author: Schlumpf (Guest)
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What do you want?
An integer which can store values in the range from 0 to x ?
or do you want to have a signal that contains x bits?

e.g.
integer range 0 to 1023 will "produce" a 10bit wide Signal which can 
contain values from 0 to 1023

std_logic_vector(1023 downto 0) will "produce" a 1024bit wide signal 
which can contain 2^1024 different binary values (0 to something very 
very large)

Author: Vinayak S. (vinayak_s)
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Its about 64800*16-bit and I need it for 8 signals/array in VHDL....

Author: Lothar Miller (lkmiller) (Moderator)
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Vinayak S. wrote:
> Its about 64800*16-bit
1.3 MBits embedded memory nowadays is in every upper range FPGA.
WHICH one do you use?

> and I need it for 8 signals/array in VHDL....
WHAT is your actual problem? WHAT task do you have to solve?

Vinayak S. wrote:
> I stack in designing pls help me.....
HOW could anyone help you? You don't answer any question, instead you 
only repeat useless facts like a mantra...

Author: Vinayak S. (vinayak_s)
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I`m using "Spartan 3A DSP".

I require memory of 64800*16*8=7Mbits......

Author: Lothar Miller (lkmiller) (Moderator)
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Vinayak S. wrote:
> I require memory of 64800*16*8=7Mbits......
so you will have to connect it externally. And of course you cannot 
implement that simply with one line of code in your VHDL description. 
Instead you must implement a RAM controller to access the external 
memory.

But: maybe you simply overestimate your secret problem...

> I require memory of 64800*16*8=7Mbits......
For what? Where does the data come from? Where does it go to? In what 
way must the data be manipulated? What data rates do you need on the 
whole system? 5 questions waiting for at least 5 answers.

Author: Vinayak S. (vinayak_s)
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I`m designing interleaver which does`t have input output formule. Means 
if first bit comes it should be place in 100th positon like that or 
output first bit at 100th place... In a system like that 64800 bits need 
to interleave before sending. previously I store it in signal but which 
not synthesize so i think for RAM/ROM...

here also got memory problem there are 8 different interleaving methods. 
Means 64K into 8 different file(to store data).

Author: dden (Guest)
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Hi,
What the heck should this be?
and why you need 8x64k for that, if its a temporary buffer you'll need 
it just once.
And why do you need a FPGA for that?

Author: Vinayak S. (vinayak_s)
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Its a part of project of DVB-T2. I have to save all values no option.

Author: Lattice User (Guest)
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Vinayak S. wrote:
> Its a part of project of DVB-T2. I have to save all values no option.

DVB-T2 ist the most komplex existing TV broadcast standard. Trying to 
implement it on a Spartan3A is akin trying to build a Formula I racing 
car using a Tata chassis.

Vinayak S. wrote:
> I`m using "Spartan 3A DSP".
>
> I require memory of 64800*16*8=7Mbits......

The largest Spartan3A DSP has only about 2Mbit block ram.

Author: dden (Guest)
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Hello,
just looked at the dvb-t2 standart, are you implementing a FECFRAME 
Bit-Interleaver?

Author: Vinayak S. (vinayak_s)
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Yes, I`m implimenting a "Bit Interleaver"...

I also refereeing same PDF only... I also implemented Interleaver but 
which not synthesizing for large buffer I used and I asked solution for 
many: what they told is go with RAM/ROM implementation but now facing 
problem of momory.. for differnt Nldpc or Qldpc, values to be interleav 
is change. so only I`m asking is there any other way of implementation 
or how effectively use RAM/ROM....


pls refer figure attached........

: Edited by User

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