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Forum: FPGA, VHDL & Verilog Signal cannot be synthesized


Author: Marko Adžić (markanjski)
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Hi guys,
I have to write a program in VHDL language in the Xilinx development 
environment, which later need to load the FPGA. Checking syntax (Check 
Syntax) throw a couple of errors. I solve them. Starting procedure 
Configure Device (iMPACT). And then I get the message:
   "Signal wtp cannot be synthesized, bad synchronous description."
Please someone help me. Sorry for bad English. This is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    Port ( cp, o1, o2, rst : in  STD_LOGIC;
           piz, wt : out  STD_LOGIC;
        seg : out std_logic_vector (6 downto 0);
        cet : out std_logic_vector (3 downto 0)
        );
end main;

architecture behavioral of main is
signal broj : integer range 0 to 30;
signal seg1, seg2 : std_logic_vector (6 downto 0);
signal cpd : std_logic;


begin
s1 : entity work.djelitelj port map(cp, cpd);
s2 : entity work.buzzer port map(cp, broj, piz);
s3 : entity work.numbers port map(cp, broj, seg1, seg2);
s4 : entity work.display port map(cp, seg1, seg2, seg, cet);

process(cp, o1, o2, rst)
variable e, q : integer range 0 to 2;
variable wtp : std_logic;
variable brnew : integer range -30 to 30;
begin

if(rst'event and rst='1')then 
   brnew:=-broj;
end if;

if(o1'event and o1='1' and e=0)then
   q:=1;
elsif(o1'event and o1='1' and e=1)then
   wtp:='1';  
  e:=0;
end if;  

if(o2'event and o2='1' and q=1)then
   brnew:=1;
  wtp:='0';
  q:=0;
elsif(o2'event and o2='1' and q=0)then
   e:=1;
end if;  



wt<=wtp;
broj<=broj+brnew;
brnew:=0;
end process;
end behavioral;


Author: Lothar Miller (lkmiller) (Moderator)
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Marko Adžić wrote:
> "Signal wtp cannot be synthesized, bad synchronous description."
And thats only the tip of an iceberg...

First lets get clear what components you have inside a FPGA for your own 
Hardware. Its fairly simple, there are only two of them:
1. Logic Cells (LUTs)
2. D-Flipflops
With those two components the synthesizer must try to implement your 
hardware description.

And now lets have a look at your code:
elsif(o1'event and o1='1' and e=1)then
   wtp:='1';  
   e:=0;
end if;  

if(o2'event and o2='1' and q=1)then
   brnew:=1;
   wtp:='0';
   q:=0;
:
In VHDL a 'event means: implement a D flipflop on the following signals. 
So wtp will be implemented as a D flipflop. And what does a D flipflop 
look like? How many clock inputs does it have? Whey does the synthesizer 
fail trying to implement wtp as a D flipflop?

Going one step back I can say: your description is obviuosly from a 
software programmer first time trying to do VHDL. Where did you find 
that extensive use of variables? Who told you to use 5 different clocks 
in 1 process? Where did you find this curious way to describe clock 
enables?

: Edited by Moderator

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