1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.std_logic_unsigned.all;
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4 |
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5 | entity uart is
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6 | port (
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7 | reset :in std_logic;
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8 | txclk :in std_logic;
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9 | ld_tx_data :in std_logic;
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10 | tx_data :in std_logic_vector (7 downto 0);
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11 | tx_enable :in std_logic;
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12 | tx_out :out std_logic;
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13 | tx_empty :out std_logic;
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14 | rxclk :in std_logic;
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15 | uld_rx_data :in std_logic;
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16 | rx_data :out std_logic_vector (7 downto 0);
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17 | rx_enable :in std_logic;
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18 | rx_in :in std_logic;
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19 | rx_empty :out std_logic
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20 | );
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21 | end entity;
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22 | architecture rtl of uart is
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23 | -- Internal Variables
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24 | signal tx_reg :std_logic_vector (7 downto 0);
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25 | signal tx_over_run :std_logic;
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26 | signal tx_cnt :std_logic_vector (3 downto 0);
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27 | signal rx_reg :std_logic_vector (7 downto 0);
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28 | signal rx_sample_cnt :std_logic_vector (3 downto 0);
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29 | signal rx_cnt :std_logic_vector (3 downto 0);
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30 | signal rx_frame_err :std_logic;
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31 | signal rx_over_run :std_logic;
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32 | signal rx_d1 :std_logic;
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33 | signal rx_d2 :std_logic;
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34 | signal rx_busy :std_logic;
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35 | signal rx_is_empty :std_logic;
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36 | signal tx_is_empty :std_logic;
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37 | begin
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38 | -- UART RX Logic
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39 | process (rxclk, reset) begin
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40 | if (reset = '1') then
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41 | rx_reg <= (others=>'0');
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42 | rx_data <= (others=>'0');
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43 | rx_sample_cnt <= (others=>'0');
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44 | rx_cnt <= (others=>'0');
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45 | rx_frame_err <= '0';
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46 | rx_over_run <= '0';
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47 | rx_is_empty <= '1';
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48 | rx_d1 <= '1';
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49 | rx_d2 <= '1';
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50 | rx_busy <= '0';
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51 | elsif (rising_edge(rxclk)) then
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52 | -- Synchronize the asynch signal
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53 | rx_d1 <= rx_in;
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54 | rx_d2 <= rx_d1;
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55 | -- Uload the rx data
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56 | if (uld_rx_data = '1') then
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57 | rx_data <= rx_reg;
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58 | rx_is_empty <= '1';
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59 | end if;
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60 | -- Receive data only when rx is enabled
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61 | if (rx_enable = '1') then
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62 | -- Check if just received start of frame
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63 | if (rx_busy = '0' and rx_d2 = '0') then
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64 | rx_busy <= '1';
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65 | rx_sample_cnt <= X"1";
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66 | rx_cnt <= X"0";
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67 | end if;
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68 | -- Start of frame detected, Proceed with rest of data
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69 | if (rx_busy = '1') then
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70 | rx_sample_cnt <= rx_sample_cnt + 1;
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71 | -- Logic to sample at middle of data
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72 | if (rx_sample_cnt = 7) then
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73 | if ((rx_d2 = '1') and (rx_cnt = 0)) then
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74 | rx_busy <= '0';
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75 | else
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76 | rx_cnt <= rx_cnt + 1;
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77 | -- Start storing the rx data
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78 | if (rx_cnt > 0 and rx_cnt < 9) then
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79 | rx_reg(conv_integer(rx_cnt) - 1) <= rx_d2;
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80 | end if;
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81 | if (rx_cnt = 9) then
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82 | rx_busy <= '0';
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83 | -- Check if End of frame received correctly
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84 | if (rx_d2 = '0') then
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85 | rx_frame_err <= '1';
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86 | else
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87 | rx_is_empty <= '0';
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88 | rx_frame_err <= '0';
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89 | -- Check if last rx data was not unloaded,
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90 | if (rx_is_empty = '1') then
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91 | rx_over_run <= '0';
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92 | else
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93 | rx_over_run <= '1';
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94 | end if;
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95 | end if;
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96 | end if;
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97 | end if;
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98 | end if;
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99 | end if;
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100 | end if;
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101 | if (rx_enable = '0') then
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102 | rx_busy <= '0';
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103 | end if;
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104 | end if;
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105 | end process;
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106 | rx_empty <= rx_is_empty;
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107 |
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108 | -- UART TX Logic
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109 | process (txclk, reset) begin
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110 | if (reset = '1') then
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111 | tx_reg <= (others=>'0');
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112 | tx_is_empty <= '1';
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113 | tx_over_run <= '0';
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114 | tx_out <= '1';
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115 | tx_cnt <= (others=>'0');
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116 | elsif (rising_edge(txclk)) then
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117 |
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118 | if (ld_tx_data = '1') then
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119 | if (tx_is_empty = '0') then
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120 | tx_over_run <= '0';
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121 | else
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122 | tx_reg <= tx_data;
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123 | tx_is_empty <= '0';
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124 | end if;
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125 | end if;
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126 | if (tx_enable = '1' and tx_is_empty = '0') then
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127 | tx_cnt <= tx_cnt + 1;
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128 | if (tx_cnt = 0) then
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129 | tx_out <= '0';
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130 | end if;
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131 | if (tx_cnt > 0 and tx_cnt < 9) then
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132 | tx_out <= tx_reg(conv_integer(tx_cnt) -1);
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133 | end if;
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134 | if (tx_cnt = 9) then
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135 | tx_out <= '1';
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136 | tx_cnt <= X"0";
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137 | tx_is_empty <= '1';
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138 | end if;
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139 | end if;
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140 | if (tx_enable = '0') then
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141 | tx_cnt <= X"0";
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142 | end if;
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143 | end if;
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144 | end process;
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145 | tx_empty <= tx_is_empty;
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146 |
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147 | end architecture;
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