Forum: FPGA, VHDL & Verilog Verilog or VHDL code for the attachment

Author: Nisarg Shah (shahnisarg0796)
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Hello everyone,

I am new in Verilog or VHDL and I want to make the code for Sc and Sd of 
figure 7 from the attachment which look like the waveform shown in red 
box at the bottom.
I have Spwm1 and Spwm2 with me, so can any one help me out to write the 
code for "FSM set" and "FSM reset" to get Sc and Sd as shown in red Box?
Also the red box is shown for 8 clock pulse, which are repeating after 8 
clock pulse.
The figure 6 is for transition understanding.

So please help me to write the verilog or VHDL code for that.

Thanks in advance.


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