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Forum: FPGA, VHDL & Verilog adg712 (switch) in VHDL


Author: sebgimi (Guest)
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Hi everyone!

I would like to right the code of the component ADG712 (datasheet in 
attachment), but I don't know how to do...

This is my code below (simplified):
entity adg712 is
     port(In1: in std_logic;
          S1: inout std_logic;
          D1: inout std_logic);
end adg712;

architecture archi of adg712 is

     signal out_gate: std_logic;

begin

     out_gate <= not(In1);

     S1 <= out_gate when In1 = '1' else 'z'; -- I think this part
     D1 <= out_gate when In1 = '1' else 'z'; -- is wrong

end archi;

The part I don't understand is the connection between the invert gate 
ouput and the wire S1 and D1.


Can you help me please ?

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
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sebgimi wrote:
> The part I don't understand is the connection between the invert gate
> ouput and the wire S1 and D1.
The INx pin of the ADG is a control pin for the behaviour between the 
two switch terminals Sx and Dx. The INx pin determines whether the two 
switch terminals are connected together or they are 'Z'...

> S1 <= out_gate when In1 = '1' else 'z'; -- I think this part
> D1 <= out_gate when In1 = '1' else 'z'; -- is wrong
You are very right.

> Can you help me please ?
Try google with "VHDL zero ohm". Thats a model for a bidirectional 
interconnection between two ports. You just have to tune it up a little 
and involve the control input INx...

: Edited by Moderator
Author: sebgimi (Guest)
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Thank you for your answer!

So if I understood right, I should write a thing like this:

  S1 <= D1 when In1 = '1' else 'Z';

I never use inout signal, so is this line enough or it will be better 
like this:

         S1 <= D1 when In1 = '1' else 'Z';
         D1 <= S1 when In1 = '1' else 'Z';

Thx

Author: Lothar Miller (lkmiller) (Moderator)
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Try it. Nothing of your proposals will work. It is a little more 
difficult. Thats why I added the search words for google (if you don't 
find anything try to add "Ben Cohen").

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