I'm trying to make random 4-bit number generator not repeating previous output. Can't find any reason why there is an error on code "IndexNumber <= zero;" these are some part of code: module RandomNumberGen( output reg [3:0] RandomIndex ); reg [3:0] IndexNumber [0:9]; reg [9:0] record; reg seed; integer i; parameter zero = 4'b0000; parameter one = 4'b0001; parameter two = 4'b0010; parameter three = 4'b0011; parameter four = 4'b0100; parameter five = 4'b0101; parameter six = 4'b0110; parameter seven = 4'b0111; parameter eight = 4'b1000; parameter nine = 4'b1001; IndexNumber [0] <= zero; /* makes error!! */ endmodule
and your example seems to be for simulation purposes only. try to get familiar with systemverilog and constrained randomization!
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