EmbDev.net

Forum: FPGA, VHDL & Verilog Can't fix error in Verilog


von WC J. (Company: MOLAB) (awon9108)


Rate this post
useful
not useful
I'm trying to make random 4-bit number generator not repeating previous 
output.
 Can't find any reason why there is an error on code
  "IndexNumber <= zero;"

these are some part of code:

module RandomNumberGen(

  output reg [3:0] RandomIndex

    );

reg [3:0] IndexNumber [0:9];
reg [9:0] record;
reg seed;
integer i;


  parameter   zero   = 4'b0000;
  parameter   one    = 4'b0001;
  parameter   two    = 4'b0010;
  parameter   three  = 4'b0011;
  parameter   four   = 4'b0100;
  parameter   five   = 4'b0101;
  parameter   six    = 4'b0110;
  parameter   seven  = 4'b0111;
  parameter   eight  = 4'b1000;
  parameter   nine   = 4'b1001;

  IndexNumber [0] <= zero; /* makes error!! */


endmodule

von Oswaldo (Guest)


Rate this post
useful
not useful
use "assign" when u are not within a always/initial block ;-)

von WC J. (Company: MOLAB) (awon9108)


Rate this post
useful
not useful
Oswaldo wrote:
> use "assign" when u are not within a always/initial block ;-)

thanks!!!

von Oswaldo (Guest)


Rate this post
useful
not useful
and your example seems to be for simulation purposes only. try to get 
familiar with systemverilog and constrained randomization!

Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.