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Forum: FPGA, VHDL & Verilog Need example of Verilog design with control flow hidden


Author: Rajdeep Mukherjee (Company: Oxford University) (ball3946)
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Hello,

I am working with behavioral Verilog design. Can anyone help me to get
an idea about how control flow is flattened out in Verilog and people
usually claim that control flow in Verilog is obscure and control flow 
is
encoded in Verilog in data-encoded way.

Can someone give me a small example (say a FSM, or a counter) and help 
me
to understand that how is control flow in Verilog is encoded in 
data-driven way?

I would appreciate any help in this regard.

Many thanks in advance.
Thank You.

Author: Lattice User (Guest)
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Search for

verilog obfuscator
verilog flattener

This will drown you with many commercial and free tools for the task

Author: Holger (Guest)
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Rajdeep Mukherjee wrote:
> I would appreciate any help in this regard.

Use Picoblase Code, wich commands your FSM in HDL.
So you have the hardend SOC Code, and --XY HDL FSM Case sel.

Use a external 1 Wire Rom with uniq. ser'#.


Use a scamble 2D Matrix ..
###########################
Greetings Holger.

Author: Holger Harten (holger-h-hennef)
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Rajdeep Mukherjee wrote:
> I would appreciate any help in this regard.

Hint:#1
Book 100 Power Tips --> VERILOG
from EVGENT STAVINOV google for EVGENT STAVINOV
Link:
http://www.amazon.com/100-Power-Tips-FPGA-Designer...

I got my for free.
LinK:
http://outputlogic.com/100_fpga_power_tips

#############################################################
On EVGENT STAVINOV Homepage a usefull Tips how to Flattener a
Design via Command Line Interface.
#############################################################

Hint#2:
Picoblaze - promgramm ändern ohne neue Synthese / implementierung
Link:
Beitrag "Picoblaze - promgramm ändern ohne neue Synthese / implementierung"
Link:
http://forums.xilinx.com/xlnx/board/message?board....
######################################################################## 
###
Greetings Holger.

http://www.edautils.com/Flattener.html

: Edited by User
Author: Rajdeep Mukherjee (Guest)
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Hello,

Many thanks for your reply.
I would like to clarify here that what I meant by “data-encoded way”. I 
am working with behavioral synthesizable subset of Verilog that allows 
control-flow statements like if-else and switch(case) but does not allow 
repeat, for, while, continue statements. So, in a sense, the behavioral 
code structure in Verilog has a flattened control-flow structure in it 
(without these loop constructs). This is easy to see because you can 
model the effect of while or for loops using only if-then-else and 
switch(case), but in a data-encoded way.

So, the FSM examples in Verilog has the same modeling with flattened 
control-flow. Can you please give me some more insight or references on 
this. From your experience, did you come across any behavioral Verilog 
designs that has an explicit control-flow structure which is not 
flattened.

Also, please inform whether any behavioral synthesis tool allow loop 
constructs like for, while, repeat, an forever?

Many Thanks in advance.
Looking forward.

Regards,
Rajdeep

Author: Holger (Guest)
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Hello !
Some C code that generates HDL Code.

VIVADO generates VERILOG CODE
Colin O'Flynn
Youtube-Video "Xilinx HLS #2: FPGA FIR Filter Design in C in 30 minutes (Vivado High Level Synthesis)"


Getting Started with Vivado High-Level Synthesis
https://www.youtube.com/watch?v=TwWavifI1yM

Greetings Holger.

Author: Holger (Guest)
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Vivado:

https://www.youtube.com/watch?v=TwWavifI1yM

This is for a state Engine
with exclusiv buss access to tweak the timing analyse.

Greetings Holger.

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