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Forum: FPGA, VHDL & Verilog Hardware cannot operate counter?


Author: Favero Santos (Guest)
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Hello!

I'm working with a Virtex 5. And I'm getting my "derriere" kicked.

I'm trying to do a count and accumulate variable which is later 
converted to a vector and used as an address to a RAM memory. So, the 
idea is simple:

- A integer variable (ACC) inside my process is used to count and 
accumulate;
- The ACC is casted to STD_LOGIC_VECTOR using addr_source:= 
CONV_STD_LOGIC_VECTOR(ACC,32);
- addr_source is copied to an address buffer register. The buffer feeds 
my RAM's address buffer.

- libraries used:
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

My code:
fsm_lower_operation: PROCESS (present_state)
VARIABLE addr_sink  : STD_LOGIC_VECTOR(0 TO data_width - 1) := X"00030005";
VARIABLE addr_source: STD_LOGIC_VECTOR(0 TO data_width - 1) := X"00020000";
VARIABLE acc      : INTEGER RANGE 0 TO 200000;
BEGIN
CASE present_state IS
  WHEN get_inst   =>
  AndAddr     <= (others => '0');
  AndDataOut  <= (others => '0');
  next_state  <= load_addr_A;
            
  WHEN load_addr_A       =>
  AndAddr    <= addr_source;
  AndDataOut  <= (others => '0');
  next_state   <= inc_stateA;
      
  WHEN inc_stateA =>
  AndAddr    <= (others => '0');
  AndDataOut  <= (others => '0');
  acc := CONV_INTEGER(addr_source) + 1;
  addr_source := CONV_STD_LOGIC_VECTOR(acc,32);
  next_state   <= wait_A;
            
  WHEN wait_A =>
  AndAddr    <= (others => '0');
  AndDataOut  <= (others => '0');
  next_state  <= getA;
      
  WHEN getA      =>
  AndAddr    <= (others => '0');
  AndDataOut  <= (others => '0');
  buff(0)    <= AndDataIn;
  next_state   <= load_addr_B;
          
  WHEN load_addr_B         =>
  AndAddr     <= addr_source;
  AndDataOut  <= (others => '0');
  next_state   <= inc_stateB;
          
  WHEN inc_stateB =>
  AndAddr    <= (others => '0');
  AndDataOut  <= (others => '0');
  acc := CONV_INTEGER(addr_source) + 1;
  addr_source := CONV_STD_LOGIC_VECTOR(acc,32);
  next_state   <= wait_B;
            
  WHEN wait_B =>
  AndAddr    <= (others => '0');
  AndDataOut  <= (others => '0');
  next_state  <= getB;
  
  WHEN getB      =>
  AndAddr    <= (others => '0');
  AndDataOut  <= (others => '0');
  buff(1)    <= AndDataIn;
  next_state   <= save_result;
            
  WHEN save_result         =>
  AndAddr     <= addr_sink;
  AndDataOut  <= buff(0) AND buff(1);
  next_state   <= end_state;
                
  WHEN end_state   => 
  next_state  <= end_state;
      
  WHEN OTHERS =>  NULL;
  END CASE;
END PROCESS fsm_lower_operation;

My issue

- When using the ACC process as explained above, operation doesn't work 
on hw. Simulating works perfectly.
- If I declare the first address' value as, i.e., X"00020001" and the 
next one as X"00002002" (explicit declaration) it works fine in HW and 
SW. The problem only occurs when I use a dynamic addressing. Ps. Mind 
only 16 MSbits (0001 and 0002); 16 LSBits are used as instructions.
- RAM code is OK. I used ISE template to synthesize my RAM.
- Further information: I'm also using a MicroBlaze. This FSM is part of 
a custom IP I'm working on. Communication between uBlaze and IP is based 
on PLB V46, using registers. Board ML506 Virtex 5, Xilinx.
- This is driving me crazy. Help.

Thanks!

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
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Favero Santos wrote:
> - libraries used:
> use IEEE.NUMERIC_STD.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
Nice idea. Where did you see this? Nowhere? Think: Why not?


> Simulating works perfectly.
Simulation is wrong, because the sensitivity list is incomplete:
fsm_lower_operation: PROCESS (present_state)
:
BEGIN
CASE present_state IS
  :
  WHEN inc_stateA =>
    :
    acc := CONV_INTEGER(addr_source) + 1; -- addr_source is missing in the senslist

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