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Forum: FPGA, VHDL & Verilog Assignment of two std_logic_vectors to std_logic at the same time


Author: Stephen (New to vhdl) (Guest)
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Hi all

I have two signals(std_logic_vector), one is of 32 bits and the other is 
of 8 bits.

I want this to be assigned to  two different signals(std_logic):

I want both assignment  to happen at the same time.How can it be done? 
Please help.


I tried to assign at  the rising_edge of a signal for both under 
different processes . But it didnt work.

Note : I dont have a clock.

Thanks in advance!

Author: Lothar Miller (lkmiller) (Moderator)
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Stephen (New to vhdl) wrote:
> I tried to assign at  the rising_edge of a signal for both under
> different processes . But it didnt work.
What didnt work? Show some code, or are we intended to guess a little?

> I want both assignment to happen at the same time.How can it be done?
> Note : I dont have a clock.
You must have any time information: WHEN is "the same time"? Do you have 
a latch signal or a validate signal or something else?

> Please help.
Pls give more information first. It would be the most easiest way to say 
what you want to do instead of saying how you want it to do...

Author: Schlumpf (Guest)
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In VHDL descriptions every assignment "happens" at the same time.
VHDL describes hardware. So it´s not a program that "runs" on an FPGA. 
It describes the interconnection of harware elements.

So if you write something like "A<=B" or "A <= B AND C" you describe a 
interconnection. And this structure exists at any time.
If the value of B changes the value of A changes immediately independent 
of the absolute time the change of B happens.

A <= B describes a piece of wire. After compilation of the code this 
wire EXISTS. And a signal change at the one end of the wire appears more 
or less immediately at the other end of the wire ;-)

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