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Forum: FPGA, VHDL & Verilog VHDL SELECT statement with variable number of cases


Author: Применко Леонидович (Company: SFedU) (p_k)
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I want to implement multiplexer in VHDL, with number of inputs as 
parameter like this:
ENTITY Multiplexer IS
  GENERIC (
    CONSTANT WORD_COUNT : INTEGER := 16;
  );
  PORT (
    d  : IN STD_LOGIC_VECTOR (WORD_COUNT-1 DOWNTO 0);
    sel: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    q  : OUT STD_LOGIC
  );
END Multiplexer;

If number of inputs is constant I can simply use select statement like 
this:
    with sel select q <=
        d(0) when b'00',
        d(1) when b'01',
        d(4) when b'10',
        d(3) when b'11',
         '0' when others;

But I can't do the same with variable number of inputs.
It seems to be easy to do something like this:
    with sel select q <= 
    M:  FOR i IN 0 TO WORD_COUNT-1 GENERATE
      d(i) when conv_std_logic_vector(i, sel'LENGTH),
        END GENERATE M;
            '0' when others;

But it doesn't work. I don't see any troubles why vhdl couldn't do 
something similar.

Author: PittyJ (Guest)
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Keep it simple.
The first code you will understand, if you look 2 years later on it.

And I thought, that the number of cases have to be defined at 
'synthesize'-time, because hardware has to be generated. How should it 
work with the second code?
But I might be wrong.

Author: Применко Леонидович (Company: SFedU) (p_k)
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"And I thought, that the number of cases have to be defined at
         'synthesize'-time"

    Yes. But it will be.

Author: Lothar Miller (lkmiller) (Moderator)
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Применко Леонидович wrote:
 with sel select q <=
     M:  FOR i IN 0 TO WORD_COUNT-1 GENERATE
This is not a place where a generate loop can be placed, because here 
it is in the very midst of the select statement.

Author: Iaaq Zakkari (isaaq_zakkari)
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Hi people,

i am a beginner in the world of vhdl and ModelSim and i need ur help..

i am trying to compile the following code but i doesnt work

(
...

architecture rsff1 of RSFF is


  begin

        process  is

        begin


      Q <= not(set and Q_quer) after 5 ns ;

      Q_quer <= not(reset and Q);

 --end if;
      wait;

end process;


  end architecture delta_delay;)



and i get alwayes the error: Cannot read output "Q_quer".
                   Cannot read output "Q".

is there any setting in the modelsim to make the code work?

I read sth about delta-delay..

Author: fpgakuechle (Guest)
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Iaaq Zakkari wrote:


> architecture rsff1 of RSFF is
>
>   begin
>
>         process  is
>
>         begin
>
>       Q <= not(set and Q_quer) after 5 ns ;
>
>       Q_quer <= not(reset and Q);
>
>  --end if;
>       wait;
>
> end process;
>
>   end architecture delta_delay;)
>
> and i get alwayes the error: Cannot read output "Q_quer".
>                    Cannot read output "Q".
>
> is there any setting in the modelsim to make the code work?
>
> I read sth about delta-delay..

The cause of the error messages lies in the lines of code hidden in the 
"...". I assume there is a ENTITY with a PORT list in which Q_quer and Q 
are OUTPUTs. You cannot use outputs as source of a assignment. You have 
to use signals for this.

Best regards

Author: Lothar Miller (lkmiller) (Moderator)
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Iaaq Zakkari wrote:
> and i get alwayes the error: Cannot read output "Q_quer".
>                    Cannot read output "Q".
This is a fairly clear message: you cannot read an output signal.How do 
others cope up with this kind of problem?

> is there any setting in the modelsim to make the code work?
You could do it in a quick and very dirty version this way:
port (Q      : buffer std_logic;
      Q_quer : inout std_logic; ...
Try it and think about my statement "qiuck and very dirty". And then use 
a local signal for those internal calculations...

> I read sth about delta-delay..
Lots of people read lots of things about something. Most of it has 
nothing to do with particular problems. This is also the case with the 
"delata delay" and your specific problem.

: Edited by Moderator

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