I want to implement multiplexer in VHDL, with number of inputs as
parameter like this:
1 | ENTITY Multiplexer IS
|
2 | GENERIC (
|
3 | CONSTANT WORD_COUNT : INTEGER := 16;
|
4 | );
|
5 | PORT (
|
6 | d : IN STD_LOGIC_VECTOR (WORD_COUNT-1 DOWNTO 0);
|
7 | sel: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
8 | q : OUT STD_LOGIC
|
9 | );
|
10 | END Multiplexer;
|
If number of inputs is constant I can simply use select statement like
this:
1 | with sel select q <=
|
2 | d(0) when b'00',
|
3 | d(1) when b'01',
|
4 | d(4) when b'10',
|
5 | d(3) when b'11',
|
6 | '0' when others;
|
But I can't do the same with variable number of inputs.
It seems to be easy to do something like this:
1 | with sel select q <=
|
2 | M: FOR i IN 0 TO WORD_COUNT-1 GENERATE
|
3 | d(i) when conv_std_logic_vector(i, sel'LENGTH),
|
4 | END GENERATE M;
|
5 | '0' when others;
|
But it doesn't work. I don't see any troubles why vhdl couldn't do
something similar.