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Forum: FPGA, VHDL & Verilog Simple Remote Control


Author: sam johnson (sam110)
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Hey guys. I'm new to this forum and new to VHDL. I'm trying to create a 
simple remote control with three inputs Nex, Prev and Number and two 
outputs
Channel (0-9)which has the same value as Number and Video which is 
asserted when Number is "0000". The code that I've written compiles that 
problem is that it's not giving me a right answer. Please can someone 
help me find the error in my logic?

Code (includes test bench):
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity remote is
  port( nex,clock,prev: in std_logic;
        number: in std_logic_vector(3 downto 0);
        video: out std_logic;
        channel: out std_logic_vector(3 downto 0));
end entity;

architecture arch of remote is
  signal chan:std_logic_vector (3 downto 0):=(others=>'0');
  signal vid:std_logic;
  type state is(S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
  signal current_state, next_state: state:=S0;
  begin
    process(nex,prev,number)
      begin
        if(nex='1' or prev='1') then
    case current_state is
    when S0=>
      if(nex='1' and prev='0')
      then  next_state<=S1;
            vid<='0';
            chan<="0001";
      elsif(nex='0' and prev='1')
      then  next_state<=S9;
            vid<='0';
            chan<="1001";
      elsif(nex='1' and prev='1')
      then  next_state<=S0;
            vid<='1';
            chan<="0000";
    end if;
    
    when S1=>
      if(nex='1' and prev='0')
      then  next_state<=S2;
            vid<='0';
            chan<="0010";
      elsif(nex='0' and prev='1')
      then  next_state<=S0;
            vid<='1';
            chan<="0000";
      elsif(nex='1' and prev='1')
      then  next_state<=S1;
            vid<='0';
            chan<="0001";
    end if;
    
    when S2=>
      if(nex='1' and prev='0')
      then  next_state<=S3;
            vid<='0';
            chan<="0011";
      elsif(nex='0' and prev='1')
      then  next_state<=S1;
            vid<='0';
            chan<="0001";
      elsif(nex='1' and prev='1')
      then  next_state<=S2;
            vid<='0';
            chan<="0010";
    end if;
    
    when S3=>
      if(nex='1' and prev='1')
      then  next_state<=S4;
            vid<='0';
            chan<="0100";
      elsif(nex='0' and prev='1')
      then  next_state<=S2;
            vid<='0';
            chan<="0010";
      elsif(nex='1' and prev='1')
      then  next_state<=S3;
            vid<='0';
            chan<="0011";
    end if;
    
    when S4=>
      if(nex='1' and prev='0')
      then  next_state<=S5;
            vid<='0';
            chan<="0101";
      elsif(nex='0' and prev='1')
      then  next_state<=S3;
            vid<='0';
            chan<="0011";
      elsif(nex='1' and prev='1')
      then  next_state<=S4;
            vid<='0';
            chan<="0100";
    end if;
    
    when S5=>
      if(nex='1' and prev='0')
      then  next_state<=S6;
            vid<='0';
            chan<="0110";
      elsif(nex='0' and prev='1')
      then  next_state<=S4;
            vid<='0';
            chan<="0100";
      elsif(nex='1' and prev='1')
      then  next_state<=S5;
            vid<='0';
            chan<="0101";
    end if;
    
    when S6=>
      if(nex='1' and prev='0')
      then  next_state<=S7;
            vid<='0';
            chan<="0111";
      elsif(nex='0' and prev='1')
      then  next_state<=S5;
            vid<='0';
            chan<="0101";
      elsif(nex='1' and prev='1')
      then  next_state<=S6;
            vid<='0';
            chan<="0110";
    end if;
    
    when S7=>
      if(nex='1' and prev='0')
      then  next_state<=S8;
            vid<='0';
            chan<="1000";
      elsif(nex='0' and prev='1')
      then  next_state<=S6;
            vid<='0';
            chan<="0110";
      elsif(nex='1' and prev='1')
      then  next_state<=S7;
            vid<='0';
            chan<="0111";
    end if;
    
    when S8=>
      if(nex='1' and prev='0')
      then  next_state<=S9;
            vid<='0';
            chan<="1001";
      elsif(nex='0' and prev='1')
      then  next_state<=S7;
            vid<='0';
            chan<="0111";
      elsif(nex='1' and prev='1')
      then  next_state<=S8;
            vid<='0';
            chan<="1000";
    end if;
    
    when S9=>
      if(nex='1' and prev='0')
      then  next_state<=S0;
            vid<='1';
            chan<="0000";
      elsif(nex='0' and prev='1')
      then  next_state<=S8;
            vid<='0';
            chan<="1000";
      elsif(nex='1' and prev='1')
      then  next_state<=S9;
            vid<='0';
            chan<="1001";
    end if;
end case;
else
  case number is
    
    when "0000"=>
      next_state<=S0;
      vid<='1';
      chan<="0000";
    
    when "0001"=>
      next_state<=S1;
      vid<='0';
      chan<="0001";
    
    when "0010"=>
      next_state<=S2;
      vid<='0';
      chan<="0010";

    when "0011"=>
      next_state<=S3;
      vid<='0';
      chan<="0011";

    when "0100"=>
      next_state<=S4;
      vid<='0';
      chan<="0100";

    when "0101"=>
      next_state<=S5;
      vid<='0';
      chan<="0101";

    when "0110"=>
      next_state<=S6;
      vid<='0';
      chan<="0110";

    when "0111"=>
      next_state<=S7;
      vid<='0';
      chan<="0111";

    when "1000"=>
      next_state<=S8;
      vid<='0';
      chan<="1000";
      
    when "1001"=>
      next_state<=S9;
      vid<='0';
      chan<="1001";
    when others=>
      next_state<=S0;
      vid<='1';
      chan<="0000";
      
      
      end case;
end if;

end process;

SEQ: process(clock)
begin
if clock'event and clock = '1' then
current_state <= next_state;
video<=vid;
channel<=chan;
end if;
end process SEQ;

end arch;

------------------------------------------------   
test bench:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity testbench is
end testbench;

architecture testbench of testbench is 

component remote port(nex,clock,prev: in std_logic;
        number: in std_logic_vector(3 downto 0);
        video: out std_logic;
        channel: out std_logic_vector(3 downto 0));
end component;

signal nex : std_logic := '0';
signal prev : std_logic := '0';
signal clock : std_logic := '0';
signal number : std_logic_vector(3 downto 0) := "0000";
signal video : std_logic;
signal channel : std_logic_vector(3 downto 0);

begin
  
  UUT: remote port map (nex => nex, prev => prev, clock => clock, number => number, video => video, channel => channel);
    process 
      begin
        Clock <= '0' ; wait for 20 ns;
        Clock <= '1' ; wait for 20 ns;
    end process;
    
    process
      begin
        
        number <= "0110"; nex <= '1'; prev <= '0'; wait for 30 ns;
        number <= "0110"; nex <= '0'; prev <= '1'; wait for 230 ns;
    end process;
end testbench;

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

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sam johnson wrote:
> The code that I've written compiles that problem is that it's not giving
> me a right answer.
What answer do you expect and what answer do you get?

BTW:
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