Hi,
I am a beginner in vhdl, struggling with vhdl programming. I am 
currently reading books and trying to understand code by other authors. 
i have to understand a code structure like this:

1

entity declaration

2

3

architecture behavioral of entity is

4

5

signal declarations:

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signal(0) <= '1' when signal_1(0)='0' and signal_2(0)='1' else '0';

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signal(1) <= '1' when signal_1(1)='0' and signal_2(1)='1' else '0';

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signal(2) <= '1' when signal_1(2)='0' and signal_2(2)='1' else '0';

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signal(3) <= '1' when signal_1(3)='0' and signal_2(3)='1' else '0';

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inport <=  data_in and not signal;

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signal_4(0) <= '1' when signal(0)='0' and signal_2(0)='1' else '0';

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signal_4(1) <= '1' when signal(1)='0' and signal_2(1)='1' else '0';

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signal_4(2) <= '1' when signal(2)='0' and signal_2(2)='1' else '0';

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signal_4(3) <= '1' when signal(3)='0' and signal_2(3)='1' else '0';

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inport_1 <= signal or signal_4;

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process(clk)

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do something here

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.

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.

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end  process

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end behavioral

my question is:

1)how this code will work, for behavioral part all statements execute 
concurrently, but signal_4 depends on signal so will second when-else 
would wait for signal computation?
2) how inport would be computed, concurrently or sequentially?
3)are all when else for signal computed simultaneously?
4)if i want to count how many bits of signal are turning to '1' after 
all 4 bits are computed is the 1's counter after when else for signal is 
the only way to do it? can i somehow count 1's within the when else?
5) if i want the same number of bits to go high for signal and signal_4, 
how can i do it?

I appreciate any help.
thanks