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Forum: FPGA, VHDL & Verilog MOV operation


Author: vhdl newbie (Company: none) (pranoy)
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--alu--

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    entity alu_ent is
        port(
            x,y:in std_logic_vector(7 downto 0);
            a:in std_logic_vector(2 downto 0);
            z:out std_logic_vector(7 downto 0)
             );
        end alu_ent;
        architecture alu_arch of alu_ent is
           
        signal reg_a_data : std_logic_vector(7 downto 0 );
        signal reg_b_data : std_logic_vector(7 downto 0 );    
        begin
        process(x,y,a)
        begin
            case a is
                when "000"=>
                z<=x+y;
                when "001"=>
                z<=x-y;
                when "010"=>
                reg_a_data<=y; 
                reg_b_data<=y;     
                z<="XXXXXXXX";
                when "011"=>
                z<=x and y;
                when "100"=>
                z<=x or y;
                when "101"=>
                reg_b_data<=x;
                reg_a_data<=x; 
                z<="XXXXXXXX";
                
                when others=> z<="XXXXXXXX";
            end case;
      end process;
    end alu_arch; 




--register--

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    
    entity reg_new is
        port( control:in std_logic_vector(2 downto 0);
            data_in:in std_logic_vector(7 downto 0);
            data_out:out std_logic_vector(7 downto 0)
            );
        end reg_new;
        
    architecture behav of reg_new is
        subtype cell is std_logic_vector(7 downto 0);
        type memarray is array(0 downto 0) of cell;
        signal mem:memarray;
        begin
            process(control)
                    variable ctrl:std_logic_vector(2 downto 0);
                    begin
                        ctrl:=control;
                        case ctrl is
                                                      
                            when "101"=>
                            data_out<=mem(0);
                            when "110"=>
                            mem(0)<=data_in;
                            data_out<=(others=>'Z');
                            when others=>
                            data_out<=(others=>'Z');
                        end case;
            end process;
        end behav;


--datapath--

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    entity datapath_latest is
        port(
            D1,D2:in std_logic_vector(7 downto 0);
            Dout:out std_logic_vector(7 downto 0);
            control:in std_logic_vector(2 downto 0);
            load:in std_logic_vector(2 downto 0)
             );
        end datapath_latest;
        architecture behav of datapath_latest is
        signal reg_a_data : std_logic_vector(7 downto 0 );
        signal reg_b_data : std_logic_vector(7 downto 0 );
               
        
component reg_new 

        port( control:in std_logic_vector(2 downto 0);
             data_in:in std_logic_vector(7 downto 0);
            data_out:out std_logic_vector(7 downto 0));
        end component;


 
component alu_ent
        port(
            x,y:in std_logic_vector(7 downto 0);
            a:in std_logic_vector(2 downto 0);
            z:out std_logic_vector(7 downto 0)
             );
        end component;
    begin        
    register_a : reg_new
 port map (
            data_in=>D1,
            control=>load,
            data_out => reg_a_data
          ) ;
  
  register_b : reg_new
 port map (
           data_in=>D2,
           control=>load,
           data_out => reg_b_data
          ) ;
  
  alu:alu_ent
  port map(x=>reg_a_data,
           y=>reg_b_data,
           z=>Dout,
           a=>control
           );
                      
    end behav; 



guys these are my components.
but i can't perform the move operation when i force the signals in 
modelsim.

can any one please help me with this?
how should i modify my code so that the control signals will come 
automatically?

Author: Lothar Miller (lkmiller) (Moderator)
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vhdl newbie wrote:
> but i can't perform the move operation when i force the signals in
> modelsim.
Why not? What problem do you encounter? What should happen? What does 
happen?

> i force the signals in modelsim.
Write a testbench. Thats what VHDL is made for...

vhdl newbie wrote:
 variable ctrl:std_logic_vector(2 downto 0);
            begin
               ctrl:=control;
               case ctrl is
Why the heck do you use a (absolutely and completely unnecessary) 
variable here? You could have written something like this instead:
            begin
               case control is

: Edited by Moderator
Author: vhdl newbie (Company: none) (pranoy)
Posted on:

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@Lothar Miller

thank you sir.

i did some changes to my programs.
but now i can't even compile it.

PLZ help me.

the programs are given below.
--datapath

library ieee;
    use ieee.std_logic_1164.all;
    --use ieee.std_logic_unsigned.all;
    
    entity datapath_latest is
        port(
            D1:in std_logic_vector(7 downto 0);
            D2:in std_logic_vector(7 downto 0);
            Dout:out std_logic_vector(7 downto 0);
            control:in std_logic_vector(2 downto 0);
            load:in std_logic_vector(2 downto 0)
             );
        end datapath_latest;
        
        architecture behav of datapath_latest is
        signal reg_a_data_in : std_logic_vector(7 downto 0 );
        signal reg_b_data_in : std_logic_vector(7 downto 0 );
        signal reg_a_data_out : std_logic_vector(7 downto 0 );
        signal reg_b_data_out : std_logic_vector(7 downto 0 );
        signal a_move : std_logic_vector(7 downto 0 );
        signal b_move : std_logic_vector(7 downto 0 );
        signal d1_signal : std_logic_vector(7 downto 0 );
        signal d2_signal : std_logic_vector(7 downto 0 );
        signal sel_signal : std_logic;  
            
        
component reg_new 

        port( control:in std_logic_vector(2 downto 0);
             data_in:in std_logic_vector(7 downto 0);
            data_out:out std_logic_vector(7 downto 0));
        end component;


 
component alu_ent
        port(
            x,y:in std_logic_vector(7 downto 0);
            a:in std_logic_vector(2 downto 0);
            reg_a_mov,reg_b_mov:out std_logic_vector(7 downto 0 );
            sel:in std_logic;
            z:out std_logic_vector(7 downto 0)
             );
        end component;
        
        component MUX
            port(
            d0:in std_logic_vector(7 downto 0);
            d1:in std_logic_vector(7 downto 0);
            s:in std_logic;
            y:out std_logic_vector(7 downto 0)
            );
        end component;
        
    begin
    
    mux_a : MUX
    
    port map(
    d0=>a_move,
    d1=>D1,
    s=>sel_signal,
    y=>reg_a_data_in
    );
    
    mux_b : MUX
    
    port map(
    d0=>b_move,
    d1=>D2,
    s=>sel_signal,
    y=>reg_b_data_in
    );
            
    register_a : reg_new
 port map (
            data_in=>reg_a_data_in,
            control=>load,
            data_out => reg_a_data_out
          ) ;
  
  register_b : reg_new
 port map (
           data_in=>reg_b_data_in,
           control=>load,
           data_out => reg_b_data_out
          ) ;
  
  alu:alu_ent
  port map(x=>reg_a_data_out,
           y=>reg_b_data_out,
           z=>Dout,
           reg_a_mov=>a_mov,
           reg_b_mov=>b_mov,
           a=>control,
           sel=>sel_signal
           );
                      
    end behav; 
--alu

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    entity alu_ent is
        port(
            x,y:in std_logic_vector(7 downto 0);
            a:in std_logic_vector(2 downto 0);
            reg_a_mov,reg_b_mov:out std_logic_vector(7 downto 0 );
            sel:in std_logic;
            z:out std_logic_vector(7 downto 0)
             );
        end alu_ent;
        architecture alu_arch of alu_ent is
                 
        
        begin
        process(x,y,a)
        begin
            
            case a is
                when "000"=>
                z<=x+y;
                reg_a_mov<="XXXXXXXX";
                reg_b_mov<="XXXXXXXX";
                sel<='1';
                when "001"=>
                z<=x-y;
                reg_a_mov<="XXXXXXXX";
                reg_b_mov<="XXXXXXXX";
                sel<='1';
                when "010"=>
                reg_a_mov<=y; 
                reg_b_mov<=y;     
                z<="XXXXXXXX";
                sel<='0';
                when "011"=>
                z<=x and y;
                reg_a_mov<="XXXXXXXX";
                reg_b_mov<="XXXXXXXX";
                sel<='1';
                when "100"=>
                z<=x or y;
                reg_a_mov<="XXXXXXXX";
                reg_b_mov<="XXXXXXXX";
                sel<='1';
                when "101"=>
                reg_b_mov<=x;
                reg_a_mov<=x; 
                z<="XXXXXXXX";
                sel<='0';
                
                when others=>
                 z<="XXXXXXXX";
                 reg_a_mov<="XXXXXXXX";
                reg_b_mov<="XXXXXXXX";
                sel<='1';
            end case;
      end process;
    end alu_arch; 
--register

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    
    entity reg_new is
        port( control:in std_logic_vector(2 downto 0);
            data_in:in std_logic_vector(7 downto 0);
            data_out:out std_logic_vector(7 downto 0)
            );
        end reg_new;
        
    architecture behav of reg_new is
        subtype cell is std_logic_vector(7 downto 0);
        type memarray is array(0 downto 0) of cell;
        signal mem:memarray;
        begin
            process(control)
                      begin
                        
                        case control is
                                                      
                            when "101"=>
                            data_out<=mem(0);
                            when "110"=>
                            mem(0)<=data_in;
                            data_out<=(others=>'Z');
                            when others=>
                            data_out<=(others=>'Z');
                        end case;
            end process;
        end behav;
                            
--mux

library ieee;
    use ieee.std_logic_1164.all;
    entity MUX is
        port(d0,d1:in std_logic_vector(7 downto 0);
            s:in std_logic;
            y:out std_logic_vector(7 downto 0)
            );
        end MUX;
        
        architecture MUX_arch of MUX is
            begin
          process(d0,d1,s)
          begin
                case s is
                     when '0'=>
                      y<=d0;
                     when '1'=> 
                     y<=d1;
                     when others=>
                      y<="ZZZZZZZZ";
                     end case;
     end process;
         end MUX_arch;
                 

i get the following errors when i compile the datapath.

** Error: H:/ollade_latest/datapath_latest_collage.vhd(53): Cannot 
assign to object "d1" of mode IN.
** Error: H:/ollade_latest/datapath_latest_collage.vhd(54): Cannot 
assign to object "d2" of mode IN.
** Error: H:/ollade_latest/datapath_latest_collage.vhd(58): VHDL 
Compiler exiting

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