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Forum: FPGA, VHDL & Verilog Asynchronous shift register


Author: Steve (Guest)
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Hallo all

I have the data in this pattern which I want to be shifted (32 bits) :

0x00000001
0x00000200
0x00030000
0x04000005

This data transfer happens in a single clock pulse . i.e .I get four 32 
bit data for every clock pulse (each has a single delta delay).This is 
basically a RGB data. Each 24 bit forms a pixel.

I want this data to be shifted continuously into a 24 bit register.So 
that I can create an image using the above data.

I am looking for a solution for this . Please help.

Thanks in advance
Steve.

Author: Lothar Miller (lkmiller) (Moderator)
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Steve wrote:
> I have the data in this pattern which I want to be shifted (32 bits) :
Clarify your specification. I don't have any clue with the information 
you provided...

Where does the data come from? What data format do you have? What do you 
want to do with that data? Is there a pixel clock or any other 
validation signal provided with the data stream? What data rate do you 
have?

There is no such thing like an "asynchonous shift register". So what do 
you want really?

Author: Steve (Guest)
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Hi

I have to read the data from an Interface which is in Hex Format.I dont 
have a pixel clock. I am just using the rgb data and nothing else.

I want to convert the 32 bit stream to 24 bits so that I can convert 
that into an image file.

If you see the above stream I have mentioned . The second pixel starts 
at the end of first data. And that continues. I want to separate that.

Thanks for your response.

Author: Achim S. (Guest)
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Steve wrote:
> 0x00000001
> 0x00000200
> 0x00030000
> 0x04000005

So you want to resort this into
000001
020000
000000
000300
...


That should not be too hard: you need a little state machine, which 
reads 3 32bit words, makes some intermediate storage of it and puts it 
out as 4 24bit words.

But due to the following statement, your task is impossible:

Steve wrote:
> I dont
> have a pixel clock. I am just using the rgb data and nothing else.

If there is no information, whether the actual data at the input is the 
first valid 32bit value or the second valid 32bit value (or invalid data 
as the signals are switching between the first and the second value), 
then there's no way to read in the data correctly.

Your data at least has to be synchronous to some clock, and you need 
some indicator, if you're just looking at the first or at the second 
32bit value.

Author: Lothar Miller (lkmiller) (Moderator)
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Steve wrote:
> I have to read the data from an Interface which is in Hex Format.
What interface is in hex format?

Steve wrote:
> I am looking for a solution for this
What language? I assume it is Verilog due to this term:
> (each has a single delta delay)


> This data transfer happens in a single clock pulse . i.e .I get four 32
> bit data for every clock pulse (each has a single delta delay).This is
> basically a RGB data.
So what you get each "cycle" is 128 bit of information?
> Each 24 bit forms a pixel.
Those 128 bit contain 5.33333 pixels...
Like this (i kicked off the C-isch 0x):
> 000000_01
> 0000_0200
> 00_030000
> 040000_05
And i coould continue your series like that
> 0000_0600
> 00_070000
> 080000_09
> 0000_0a00
> 00_0b0000
> 0c0000_0d
:
:

> I want this data to be shifted continuously into a 24 bit register.
Shifting is not possible without a clock. I think i mentioned that 
already...

: Edited by Moderator

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