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Forum: FPGA, VHDL & Verilog RAM read and write


Author: vhdl newbie (Company: none) (pranoy)
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library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SRAM is
generic(width:integer:=4;depth:integer:=32);
port(
Clock:in std_logic;
Enable:in std_logic;
Read:in std_logic;
Write:in std_logic;
Read_Addr:in std_logic_vector(4 downto 0);
Write_Addr: in std_logic_vector(4 downto 0);
Data_in: in std_logic_vector(3 downto 0);
Data_out: out std_logic_vector(3 downto 0));
end SRAM;

architecture behav of SRAM is
    type ram_type is array (0 to 31) of
    std_logic_vector(3 downto 0);
    signal tmp_ram:ram_type;
    begin
        process(clock,read)
            begin
                if(clock'event and clock='1') then
                    if enable='1' then
                        if read='1' then
                            data_out<=tmp_ram(conv_integer(read_addr));
                            else
                            data_out<=(data_out'range=>'Z');
                        end if;
                    end if;
                end if;
            end process;
            process(clock,write)
                begin
                    if(clock'event and clock='1') then
                        if enable='1' then
                            if write='1' then
                                tmp_ram(conv_integer(write_addr))<=data_in;
                            end if;
                        end if;
                    end if;
                end process;
            end behav;

I got this code for RAM online.

When i run it in MODELSIM the writing takes a complete clock cycle(if 
clock starts with a +ve edge) and
reading takes 1 and 1/2 clock cycles(if clock starts with a +ve edge).


could anyone explain why is it so?

and also pls give me a way to make the read and write cycle within a 
single clock cycle.

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