1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | --use ieee.std_logic_arith.all;
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4 | use ieee.std_logic_unsigned.all;
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5 | entity SRAM is
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6 | generic(width:integer:=4;depth:integer:=32);
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7 | port(
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8 | Clock:in std_logic;
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9 | Enable:in std_logic;
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10 | Read:in std_logic;
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11 | Write:in std_logic;
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12 | Read_Addr:in std_logic_vector(4 downto 0);
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13 | Write_Addr: in std_logic_vector(4 downto 0);
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14 | Data_in: in std_logic_vector(3 downto 0);
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15 | Data_out: out std_logic_vector(3 downto 0));
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16 | end SRAM;
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17 |
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18 | architecture behav of SRAM is
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19 | type ram_type is array (0 to 31) of
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20 | std_logic_vector(3 downto 0);
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21 | signal tmp_ram:ram_type;
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22 | begin
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23 | process(clock,read)
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24 | begin
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25 | if(clock'event and clock='1') then
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26 | if enable='1' then
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27 | if read='1' then
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28 | data_out<=tmp_ram(conv_integer(read_addr));
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29 | else
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30 | data_out<=(data_out'range=>'Z');
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31 | end if;
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32 | end if;
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33 | end if;
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34 | end process;
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35 | process(clock,write)
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36 | begin
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37 | if(clock'event and clock='1') then
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38 | if enable='1' then
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39 | if write='1' then
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40 | tmp_ram(conv_integer(write_addr))<=data_in;
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41 | end if;
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42 | end if;
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43 | end if;
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44 | end process;
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45 | end behav;
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I got this code for RAM online.
When i run it in MODELSIM the writing takes a complete clock cycle(if
clock starts with a +ve edge) and
reading takes 1 and 1/2 clock cycles(if clock starts with a +ve edge).
could anyone explain why is it so?
and also pls give me a way to make the read and write cycle within a
single clock cycle.
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