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Forum: FPGA, VHDL & Verilog HELP VHDL noob!


Author: michael (Guest)
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http://www.docdroid.net/5zy2/doc1.pdf.html
I don't understand why i get the errors on page 2

Author: Guest (Guest)
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There is a ';' in line 97 after '(1)' where there should be a regular 
','.

Author: michael (Guest)
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Do any of the warnings matter?

Author: Lothar Miller (lkmiller) (Moderator)
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I cannot believe my eyes: a few lines of sourcecode and warnings stuffed 
behind each other as screenshots inside a PDF file. Thats completely 
NONSENSE!
You can attach a vhdl file here and cpoy/paste the messages instead. 
Thats much faster, one can search the text and format it the way he 
likes...

And now to the warnings: what do you do with the port B in the concerned 
lines? Its fairly easy to see: you assign a inverted signal by using the 
function not(). Thats not allowed in VHDL. Do the negation outside the 
port assignemt.

BTW: why do you do this simple piece of hardware in such a complicated 
way?

: Edited by Moderator
Author: Nikolaos Kavvadias (Company: http://www.nkavvadias.com) (nikolaos_k)
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Hi OP,

this is a really ugly way to present your problem.

Can you give more details on the overall context. Is your homework/task 
just this simple logic circuit or is this part of something bigger?

Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com

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