Forum: FPGA, VHDL & Verilog Reading Verilog Code

Author: Syed Huq (gamingx)
Posted on:

Rate this post
0 useful
not useful
Hi guys,

I'm familiar with using FPGAs and with Verilog and VHDL so I'm able to 
do a fair bit with it. But I have difficulty when reading somebody 
else's code. For example, I have this large project which uses an FPGA 
and it already contains the code so I'm trying to figure out how the 
code actually works, but I'm not sure where to start with it. Any 
guidelines or tips would be appreciated!

Author: Duke Scarring (Guest)
Posted on:
Attached files:

Rate this post
0 useful
not useful
In such a case I start with generating a hierarchy diagram to get an 
The next step is to identify the dataflow.
Or vice versa :-)



Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.