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Forum: FPGA, VHDL & Verilog Verilog : Division of 2 numbers (8bit)


Author: Munteanu Vlad (Company: Automatic Control) (popdog22)
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I have to divide two 8 bit numbers using Verilog(homework). The module I 
have to use is this one:

module divider(
output reg[7:0] q,
output reg[7:0] r,
input [7:0] a,b);
endmodule
where a=b*q+r

I am told that I can use SRT, Newton-Raphson or Goldschmidt algorithms 
to solve it, but i don't understand how they work...

Any help pls?

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Author: Mirco (Guest)
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Hi,

the Newton-Algo is easy to understand there are also Tutorials on 
youtube.
If the Verilog Code dont have to be synthesizable u also could use the 
Goldschmidt algo on wikipedia.
Normaly got help if you have a specific Problem with Verilog but i guess 
nobody will do your homework.

Author: Hans-werner M. (hanswerner)
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Mirco wrote:
> If the Verilog Code dont have to be synthesizable u also could use the
> Goldschmidt algo on wikipedia.
Warum ist der Goldschmidt Algorithmus nicht synthetisierbar ? Das konnte 
ich dem Wikipedia Artikel jetzt nicht entnehmen. Welche Gründe sprechen 
dagegen ?

Author: Lothar Miller (lkmiller) (Moderator)
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Hans-werner M. wrote:
> Mirco wrote:
>> If the Verilog Code dont have to be synthesizable u also could use the
>> Goldschmidt algo on wikipedia.
> Warum ist der Goldschmidt Algorithmus nicht synthetisierbar ? Das konnte
> ich dem Wikipedia Artikel jetzt nicht entnehmen. Welche Gründe sprechen
> dagegen ?
This is an english forum. Please answer in english.

BTW:
Bitte nicht Plenken!
(I'm sorry to say that "Plenken" is up to now not defined within english 
language: http://en.wikipedia.org/wiki/Plenken)

Author: Mirco (Guest)
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Hi,

i ment that u can take the c implementation without having a lot of work 
to do.

Author: Munteanu Vlad (Company: Automatic Control) (popdog22)
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Micro, I've studied the algorithms, and now I have the pseudocode of 
RADIX-2 Division of 2 numbers in floating point. But I need the 
pseudocode in fixed point, and I cand't figure it out. However i put it 
in Xilinx, I get scrambled values when to simulate.

I have attached the pseudocode and the verilog code.

Thanks.

Author: Nikolaos Kavvadias (Company: http://www.nkavvadias.com) (nikolaos_k)
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Hi,

your code (apart from certain mistakes) is not synthesizable. The best 
approach is to implement it as an ASMD/FSMD (Finite State Machine with 
Datapath), what you attempt will not produce meaningful hardware (or any 
hardware that is).

You can have a look to exemplary FSMDs, at my website:
http://www.nkavvadias.com/hercules/

I am the sole developer of HercuLeS, a novel high-level synthesis tool. 
What you can find on this page is some info on HercuLeS plus some 
examples. There is also a FREE download for Windows 7 64-bit and Linux 
32-/64-bit but after you are on your own. The FREE version does not 
cover floating-point and fixed-point designs, you have to pay a minimal 
sum of around 2k EUR per year (including unlimited support) for this.

Let me know if either you or your teacher/mentor is interesting in using 
HercuLeS.

Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com

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