Hi all I have a Timing measure module which Outputs a Text File with the following : (VHDL) Signal Unit pixel clock ps pixel clock freq Hz h_frontporch pixel clock h_back porch pixel clock h_pulse width pixel clock hsync pixel clock vsync hsync v_frontporch hsync v_back porch hsync v_pulsewidth hsync The input is RGB data (27 downto 0) which includes p_clk , de , hsync,vsync , and rgb (each 8 bits) Please help me to find the logic with these Inputs. Thanks all.
Nitish wrote: > I have a Timing measure module Pls show your VHDL code. > I have a Timing measure module which Outputs a Text File with the > following : So this module is intended only for simulation?
VHDL Code :
1 | architecture timing_measure_arc of timing_measure is |
2 | |
3 | |
4 | |
5 | constant C_CLK_PERIOD : time := 30 ns ; |
6 | |
7 | -- Signals -----------------------------------------------------------------
|
8 | signal de_set_reg : natural ; |
9 | signal de_reset_reg : natural ; |
10 | signal hsync_reg : natural ; |
11 | signal vsync_reg : natural ; |
12 | signal hfp_reg :natural ; |
13 | signal hbp_reg :natural ; |
14 | signal hpw_reg :natural ; |
15 | signal vfp_reg :natural ; |
16 | signal vbp_reg :natural ; |
17 | signal vpw_reg :natural ; |
18 | |
19 | alias p_clk is rgb_mux_data (27); |
20 | alias de_t is rgb_mux_data (26); |
21 | alias hsync_t is rgb_mux_data (25); |
22 | alias vsync_t is rgb_mux_data (24); |
23 | alias rgb_mux_data(23 downto 0) is rgb_mux_data (23 downto 0); |
24 | |
25 | begin
|
26 | -- Asynchrouns Assignments ---------------------------------------------------
|
27 | |
28 | -- Synchrouns Assignments ----------------------------------------------------
|
29 | t_pclk <= pclk_reg ; |
30 | de_set <= de_set_reg ; |
31 | de_reset <= de_reset_reg ; |
32 | hsync <= hsync_reg ; |
33 | vsync <= vsync_reg ; |
34 | h_fp <= hfp_reg; |
35 | h_pb <= hbp_reg; |
36 | h_pw <= hpw_reg; |
37 | v_fp <= vfp_reg; |
38 | v_pb <= vbp_reg; |
39 | v_pw <= vpw_reg; |
40 | -- Processes -----------------------------------------------------------------
|
41 | |
42 | |
43 | p_timing_measure : process (reset,p_clk) |
44 | |
45 | |
46 | begin
|
47 | if reset = '1' then |
48 | f_pclk <= '0'; |
49 | t_pclk <= '0'; |
50 | de_set <= '0'; |
51 | de_reset <= '0'; |
52 | h_fp <= '0'; |
53 | h_pb <= '0'; |
54 | h_pw <= '0'; |
55 | hsync <= '0'; |
56 | v_fp <= '0'; |
57 | v_pb <= '0'; |
58 | v_pw <= '0'; |
59 | vsync <= '0'; |
60 | de_set_reg <= 0; |
61 | de_reset_reg <= 0; |
62 | hsync_reg <= 0; |
63 | vsync_reg <= 0; |
64 | hfp_reg<= 0; |
65 | hbp_reg<= 0; |
66 | hpw_reg<= 0; |
67 | vfp_reg<= 0; |
68 | vbp_reg<= 0; |
69 | vpw_reg<= 0; |
70 | |
71 | elsif reset = '0' then |
72 | if rising_edge(p_clk) then |
73 | |
74 | t_pclk <= C_CLK_PERIOD * 1000 ; |
75 | |
76 | f_pclk <= (1/t_pclk) * 1000000 ; |
77 | |
78 | |
79 | if( de_t = '1' and rising_edge(p_clk)) then |
80 | loop
|
81 | de_set_reg := de_set_reg +1 ; |
82 | end loop ; |
83 | else
|
84 | loop
|
85 | de_reset_reg := de_reset_reg + 1 ; |
86 | end loop ; |
87 | |
88 | if (hsync_t = '0' and rising_edge(p_clk)) then |
89 | loop
|
90 | hsync_reg := hsync_reg +1 ; |
91 | end loop ; |
92 | end if ; |
93 | |
94 | if(vsync_t = '0' and falling_edge (hsync_t) ) then |
95 | loop
|
96 | vsync_reg := vsync_reg +1 ; |
97 | end loop ; |
98 | end if ; |
99 | |
100 | |
101 | |
102 | wait until(de_t = 0) |
103 | while (hsync_t = 1) loop |
104 | wait until rising_edge(p_clk) ; |
105 | |
106 | hfp_reg := hfp_reg + 1 ; |
107 | end loop ; |
108 | |
109 | wait until(hsync_t = 1) |
110 | while (de_t = 0) loop |
111 | wait until rising_edge(p_clk) ; |
112 | |
113 | hbp_reg := hbp_reg + 1 ; |
114 | end loop ; |
115 | |
116 | if (de_t = 0) |
117 | wait until(hsync_t = 0) |
118 | while (hsync_t= 0) loop |
119 | wait until rising_edge(p_clk) ; |
120 | |
121 | hpw_reg := hpw_reg + 1 ; |
122 | end loop ; |
123 | end if ; |
124 | |
125 | |
126 | |
127 | |
128 | |
129 | wait until(de_t = 0) |
130 | while (vsync_t = 1) loop |
131 | wait until falling_edge(hsync_t) ; |
132 | |
133 | vfp_reg := vfp_reg + 1 ; |
134 | end loop ; |
135 | |
136 | wait until(vsync_t = 1) |
137 | while (de_t = 0) loop |
138 | wait until falling_edge(hsync_t) ; |
139 | |
140 | vbp_reg := vbp_reg + 1 ; |
141 | end loop ; |
142 | |
143 | if (de_t = 0) |
144 | wait until(vsync_t = 0) |
145 | while (vsync_t= 0) loop |
146 | wait until falling_edge(hsync_t) ; |
147 | |
148 | vpw_reg := vpw_reg + 1 ; |
149 | end loop ; |
150 | end if ; |
151 | |
152 | end if; |
153 | |
154 | end process p_timing_measure ; |
Yes for now, its only for simulation
:
Edited by Admin
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