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Forum: FPGA, VHDL & Verilog synthesisable vhdl codes


Author: vhdl newbie (Company: none) (pranoy)
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hi guys,

first of all i'm new to vhdl

my project is to build a microcontroller.

my project guide said to search about synthesisable vhdl codes.

please help me.

Author: Klappskalli (Guest)
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you failed!

Author: Lothar Miller (lkmiller) (Moderator)
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pranoy tm wrote:
> first of all i'm new to vhdl
> my project is to build a microcontroller.
What time schedule do you have?
You won't believe it, but in a microcontrollers design there are dumped 
many man-years of work. And those guys are professionals, not beginners!

> my project guide said to search about synthesisable vhdl codes.
Thats a good idea if you want a real uC running on a FPGA.

> please help me.
Whats your question?

A little hint: start with a blinking LED, then a chasing light, and so 
on...

Author: Schlumpf (Guest)
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Well, then let´s start with the core of your microcontroller.

http://en.wikipedia.org/wiki/LEON

too complicated?? then..

Lothar Miller wrote:
> start with a blinking LED, then a chasing light, and so
> on...

Author: TM (Guest)
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Lothar Miller wrote:
> A little hint: start with a blinking LED, then a chasing light, and so
> on...

Hello,

Yes I think the right way is to start with little things. But a 
processor also consists of easy parts.

So first start to learn how to describe:

- Multiplexers
- combinatorial Logic
- An ALU should be possible
- State Machines

At the moment I am writing a simple CPU in VHDL
At the moment it is in process but if you want to you can look ath the 
source.

http://www.blog-tm.de/?p=80

Author: vhdl newbie (Company: none) (pranoy)
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guys

first of all it's a 4 bit microcontroller with just 8 basic 
instructions(+,-,and,or,xor,...).

I have done some basic programs like MUX,DEMUX,full adder,carry look 
ahead adder,decoder,encoder,2's complement,counter

I used modelsim as a simulator.

i also designed a simple alu.

MY QUESTION IS

i wrote the alu with statements like

c=a+b;

can i do like this if i'm to run it on an actual FPGA?

Author: PittyJ (Guest)
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>> i wrote the alu with statements like
>>
>> c=a+b;

Forget variables and use signals, if you work on real hardware.
So I think, you have to restart everything.

Author: Lothar Miller (lkmiller) (Moderator)
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pranoy tm wrote:
> i wrote the alu with statements like
> c=a+b;
This is no VHDL statement.

> can i do like this if i'm to run it on an actual FPGA?
Yes you can use +,-,* without any restrictions. But if you want to 
implement a / then you have to start thinking...

BTW: you can read such basic things in almost every new book about "VHDL 
for FPGAs".

> I have done some basic programs
VHDL is NOT a programming language!
I would say that you have done some basic designs on a FPGA.

Author: vhdl newbie (Company: none) (pranoy)
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library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    entity alu_ent is
        port(
            x,y:in std_logic_vector(3 downto 0);
            a:in std_logic_vector(2 downto 0);
            z:out std_logic_vector(3 downto 0)
            );
        end alu_ent;
        architecture alu_arch of alu_ent is
        begin
        process(x,y,a)
        begin
            case a is
                when "000"=>z<=x+y;
                when "001"=>z<=x-y;
                when "010"=>z<=not(x);
                when "011"=>z<=x and y;
                when "100"=>z<=x or y;
                when "101"=>z<=x xor y;
                when others=> z<="XXXX";
            end case;
                    
      
    end process;
    end alu_arch; 

can i execute this on an actual FPGA?

Author: PittyJ (Guest)
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Where is the clock?

Author: TM (Guest)
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vhdl newbie wrote:
> library ieee;
>     use ieee.std_logic_1164.all;
>     use ieee.std_logic_unsigned.all;
>     entity alu_ent is
>         port(
>             x,y:in std_logic_vector(3 downto 0);
>             a:in std_logic_vector(2 downto 0);
>             z:out std_logic_vector(3 downto 0)
>             );
>         end alu_ent;
>         architecture alu_arch of alu_ent is
>         begin
>         process(x,y,a)
>         begin
>             case a is
>                 when "000"=>z<=x+y;
>                 when "001"=>z<=x-y;
>                 when "010"=>z<=not(x);
>                 when "011"=>z<=x and y;
>                 when "100"=>z<=x or y;
>                 when "101"=>z<=x xor y;
>                 when others=> z<="XXXX";
>             end case;
>
>
>     end process;
>     end alu_arch;
>
> can i execute this on an actual FPGA?


Yes you can do this on an actual fpga. But the others statement should 
result in a defined state like z<= x+y or z <= "0000"

Scince an alu is combinatorial you do not need a clock here but at some 
point in the design.

best regards

Tobias

Author: Lothar Miller (lkmiller) (Moderator)
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vhdl newbie wrote:
> use ieee.std_logic_unsigned.all;
>                 when "000"=>z<=x+y;
>                 when "001"=>z<=x-y;
Here you should implement any kind of rollover handling (in case of 
overflow or underflow)...

Author: Schlumpf (Guest)
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vhdl newbie wrote:
> can i execute this on an actual FPGA?

No, you cannot.
Because VHDL ist not executed on an FGPA.
VHDL describes hardware.

Author: vhdl newbie (Company: none) (pranoy)
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thank you all. :)

TM wrote:
> Yes you can do this on an actual fpga. But the others statement should
> result in a defined state like z<= x+y or z <= "0000"

what should i do to get high impedance output?



Lothar Miller wrote:
>>                 when "000"=>z<=x+y;
>>                 when "001"=>z<=x-y;
> Here you should implement any kind of rollover handling (in case of
> overflow or underflow)...


how can i get the carry?
should i use a 4 bit adder instead of the '+' sign?

Author: Lothar Miller (lkmiller) (Moderator)
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vhdl newbie wrote:
> what should i do to get high impedance output?
(Why) do you need high impedance output?


>>> when "000"=>z<=x+y;
>>>  when "001"=>z<=x-y;
>> Here you should implement any kind of rollover handling (in case of
>> overflow or underflow)...
> how can i get the carry?
Think a little!
And the add one leading bit to recognize overflow/underflow...

> should i use a 4 bit adder instead of the '+' sign?
What will you gain if you do so?

Author: FPGA-Professional (Guest)
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I guess he needs "dont care" insted of high Z.

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