Hi there, I have written a code of an FSM using VHDL and used GHDL to compile it. The error that is prompting is hello.vhdl:25:50: "<=" or ":=" expected instead of then. I have attached the file of the code. Here I paste it too:
1 | library IEEE; |
2 | use IEEE.std_logic_1164.all; |
3 | |
4 | entity ex19 is |
5 | Port( |
6 | X, SET: in std_logic; |
7 | clk:in std_logic; |
8 | Y: out std_logic_vector (0 to 1); |
9 | Z2: out std_logic); |
10 | end ex19; |
11 | |
12 | architecture ex19arc of ex19 is |
13 | |
14 | type stateType is(ST0, ST1, ST2); |
15 | Signal PS, NS: StateType; |
16 | |
17 | begin
|
18 | |
19 | sync_proc: process (CLK, NS, SET) |
20 | |
21 | |
22 | Begin
|
23 | If (SET = '1') then |
24 | PS <= ST2; |
25 | elseif (rising_edge(clk)) then |
26 | PS <= NS; |
27 | else PS <= PS; |
28 | end if; |
29 | End process sync_proc; |
30 | |
31 | comb_proc: process (PS,x) |
32 | |
33 | Begin
|
34 | case PS is |
35 | when ST0 => |
36 | Z2 <= '0'; |
37 | if (x = '0') then |
38 | NS <= ST0; |
39 | else NS <= ST1; |
40 | end if; |
41 | when ST1 => |
42 | Z2 <= '0'; |
43 | if (x = '0') then |
44 | NS <= ST0; |
45 | else
|
46 | NS <= ST2; |
47 | end if; |
48 | when ST2 => |
49 | if (x = '0') then |
50 | NS <= ST0; |
51 | Z2 <= '0'; |
52 | else
|
53 | NS <= ST2; |
54 | Z2 <= 1; |
55 | end if; |
56 | |
57 | end case; |
58 | end process; |
59 | |
60 | with PS select |
61 | Y <= "00" when ST0, |
62 | "10" when ST1, |
63 | "11" when ST2, |
64 | "00" when others; |
65 | end ex19arc; |