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Forum: FPGA, VHDL & Verilog generic register lfsr


Author: siwar (Guest)
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good morning
I want to program a vhdl code wich work with input , output and selector 
pointing a generic component. this component is a registre lfsr each 
time it take new parameter generator polynomial

it joined my idea of implementation

And this my first think of code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
use STD.TEXTIO.ALL;
library WORK;
use WORK.pkgg.ALL;
entity scrambler is
    Port ( e : in  STD_LOGIC_VECTOR (29 downto 0);
           Sel : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (29 downto 0));
end scrambler;
architecture Behavioral of scrambler is

   SIGNAL rst_n :   std_logic;
   SIGNAL clk   :   std_logic;
   SIGNAL dout  :  std_logic_vector(29 downto 0);

    CONSTANT width  : integer     := 30;
    CONSTANT length : integer     := 31;         -- length of the register
    CONSTANT taps   : T_LFSR_TAPS16 := (31, 27, 26, 25, 22, 21, 19, 18, 17, 16, 10, 7, 6, 5, 3, 2);

           component genlfsr 
           generic (
    width  : integer     := 30;
    length : integer     := 31;         
    taps   : T_LFSR_TAPS16 := (31, 27, 26, 25, 22, 21, 19, 18, 17, 16, 10, 7, 6, 5, 3, 2)
    );

    port ( 
    rst_n : in  std_logic;
    clk   : in  std_logic;
    dout  : out std_logic_vector(29 downto 0) 
          );
  end component;

bgin

U1: entity work.genlfsr(behavioral) 
    generic map (width => width ,length => length ,taps => taps)
    port map(rst_n => rst_n ,clk => clk ,dout =>dout);

process (dout ) is
   
   begin
 
 s(29 downto 29-dout'high) <= dout;

 end process;
end Behavioral;

So I don't understand how to make a generic registre lfsr with different 
value

Author: siwar (Guest)
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please help me

Author: Lothar Miller (lkmiller) (Moderator)
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siwar wrote:
> So I don't understand how to make a generic registre lfsr with different
> value
What do you mean with a "different value"?
Different taps?

siwar wrote:
> 12:33
siwar wrote:
> 13:02
> please help me
Please wait some minutes. At least half an hour. This is not a hotline.

And then post your own suggestion of a solution for the desired 
component "genlfsr". Then we can discuss the design. But no one is 
intended to do all of your job, bcause its your homework...


And additionally: one post is enough! I have deleted the other one.

Author: siwar (Guest)
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I apologize for the inconvenience
I'm sorry

Author: anynomous (Guest)
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you should describe what you want,

i simply cannot imagine what is intended

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