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Forum: FPGA, VHDL & Verilog Error in VHDL


Error in VHDL
von vhdl n. (Company: none) (pranoy)

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library ieee;

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    use ieee.std_logic_1164.all;

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    entity enc_ent is

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        port(enable:in std_logic;

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            d:in std_logic_vector(7 downto 0);

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            y:out std_logic_vector(2 downto 0)

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            );

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        architecture enc_arc of enc_ent is

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             begin

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             process(enable,d)

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             begin

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            if(enable='1') then

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            case d is

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            when "00000001"=> y<="000";

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            when "00000010"=> y<="001";

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            when "00000100"=> y<="010";

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            when "00001000"=> y<="011";

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            when "00010000"=> y<="100";

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            when "00100000"=> y<="101";

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            when "01000000"=> y<="110";

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            when others=> y<="111";

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            end case;

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                else 

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                y<="UUU";

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            end if;

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            end process;

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     end enc_arc;


this is my code

but i get this error message.

encoder.vhd(9): near "architecture": expecting: END


can u tell what is the problem?

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Re: Error in VHDL
von Klappskalli (Guest)

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end of entity is missing

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Re: Error in VHDL
von vhdl n. (Company: none) (pranoy)

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thanks

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