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Forum: FPGA, VHDL & Verilog Error in VHDL


Author: vhdl newbie (Company: none) (pranoy)
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library ieee;
    use ieee.std_logic_1164.all;
    entity enc_ent is
        port(enable:in std_logic;
            d:in std_logic_vector(7 downto 0);
            y:out std_logic_vector(2 downto 0)
            );
            
        architecture enc_arc of enc_ent is
             begin
             process(enable,d)
             begin
            if(enable='1') then
            case d is
            when "00000001"=> y<="000";
            when "00000010"=> y<="001";
            when "00000100"=> y<="010";
            when "00001000"=> y<="011";
            when "00010000"=> y<="100";
            when "00100000"=> y<="101";
            when "01000000"=> y<="110";
            when others=> y<="111";
            end case;
                else 
                y<="UUU";
            end if;
            end process;
     end enc_arc; 

this is my code

but i get this error message.

encoder.vhd(9): near "architecture": expecting: END


can u tell what is the problem?

Author: Klappskalli (Guest)
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end of entity is missing

Author: vhdl newbie (Company: none) (pranoy)
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thanks

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