Hello,
I am just a college student, I am trying to improve my knowledge of
Verilog :) Now I am working with an Altera DE0-Nano. What I would like
to achieve is pretty simple: a shift register that shifts to the left
with one button and to the right with another one. My first draft was
the following one, but it did not work.
1 | module led_shift(UP, DOWN, RES, CLK, LED);
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2 | input UP, DOWN, RES, CLK;
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3 | output reg [7:0] LED;
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4 | reg [7:0] STATE;
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5 |
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6 | always@(negedge DOWN or negedge UP or negedge RES)
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7 | begin
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8 | if(!RES)
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9 | begin
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10 | STATE <= 8'b00010000;
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11 | end
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12 | else
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13 | begin
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14 | STATE <= UP ? STATE>>1 : STATE<<1;
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15 | end
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16 | end
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17 |
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18 | always @ (posedge CLK)
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19 | begin
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20 | LED <= STATE;
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21 | end
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22 | endmodule
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The problem was, that it was not clear for the synthesizer to know how
to control STATE with the 3 asynchronous control signals, so I was told
to use the technique of clock domain crossing. To simplify more, I
decided to work with only the left shift, and this is the second draft.
1 | module led_shift(UP, DOWN, RES, CLK, LED);
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2 |
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3 | input UP, DOWN, RES, CLK;
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4 | output reg [7:0] LED;
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5 | reg [7:0] STATE;
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6 | reg pre_sync_UP, sync_UP;
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7 |
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8 |
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9 | always @(posedge CLK) begin
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10 | if(!RES) begin
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11 | LED = 8'b00000001;
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12 | end
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13 | else begin
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14 | pre_sync_UP <= UP;
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15 | sync_UP <= pre_sync_UP;
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16 | LED <= STATE;
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17 | end
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18 | end
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19 |
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20 | always@(sync_UP or pre_sync_UP) begin
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21 | if(sync_UP && !pre_sync_UP) begin
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22 | STATE <= LED << 1;
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23 | end
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24 | else begin
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25 | STATE <= LED;
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26 | end
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27 | end
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28 |
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29 |
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30 | endmodule
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(Istead of
I also tried the xor, but it did not work)
Unfortunately it does not work at all, after putting the RES at 1, it
seems that the shift is always performed, even without pressing the
button. I can not see why, though. Someone can help me?
Thanks!