EmbDev.net

Forum: FPGA, VHDL & Verilog Project Navigator ISE


Author: siwar dammak (Company: ISIMSfax) (siwardammak)
Posted on:

Rate this post
0 useful
not useful
I want an error when I examine my vhdl program with Project NAvigator 
ISE this is the error :
"Bitgen:342 - This design contains pins which have locations (LOC) that 
are not user-assigned or I/O Standards (IOSTANDARD) that are not 
user-assigned.  This may cause I/O contention or incompatibility with 
the board power or connectivity affecting performance, signal integrity 
or in extreme cases cause damage to the device or the components to 
which it is connected.  To prevent this error, it is highly suggested to 
specify all pin locations and I/O standards to avoid potential 
contention or conflicts and allow proper bitstream creation.  To demote 
this error to a warning and allow bitstream creation with unspecified 
I/O location or standards, you may apply the following bitgen switch: -g 
UnconstrainedPins:Allow"

please help me
thanks

Author: Rosa-Kleidchen (Guest)
Posted on:

Rate this post
0 useful
not useful
Hi,
It seems that your constraint file is not suitable. Do you use a demo 
board or something like that?
Rosa

Author: siwar dammak (Company: ISIMSfax) (siwardammak)
Posted on:

Rate this post
0 useful
not useful
No I don't use a demo board.
what is a constraint file ? how make it ?

Author: Duke Scarring (Guest)
Posted on:

Rate this post
0 useful
not useful
What FPGA you are using?

Duke

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
siwar dammak wrote:
> what is a constraint file ?
Google's not working?
https://www.google.com/search?q=constraint+file+xilinx

Author: siwar dammak (Company: ISIMSfax) (siwardammak)
Posted on:

Rate this post
0 useful
not useful
My type of FPGA is Spartan-3A xc3s700a-4fg484

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.