Dear all, Hi. I tended to design a low power 32-to-1 multiplexer and compare the DC extraxted power result with original one. I thought of tree of 2-to-1 blocks of MUXs. But not only the result does not show any improvement, but also the original MUX has lower power and higher slack time. I mean, even if I wanted to cover the increased power result with an improved PDP, it was not possible because neigther the time report has no improvement comparing to original MUX. Does any one has any idea why I can't get the results I expected? Thanks in advance
What are you talking about? More information please. What is the background of your experiment? What kind of a fpga do you use? The best way to achieve the best performance is to adapt the design to available hardware e.g. by using the dedicated slice multiplexer.
I wrote a VHDL code for two 32-to-1 MUX, one in normal form of describing the MUX and the other is using the design method of tree-form of 2-to-1 MUX blocks. I sythesized both codes with TSMC018 library with Design Compiler.Both architectures are behavioral. The base line (non-tree and non-hierarchical)32-to-1 MUX report lower power consumption compared to the tree-form one, which is in contrast with what I've studied for low power design method for MUX. [ref: http://www.cecs.uci.edu/~papers/compendium9403/papers/1997/islped97/pdffiles/t6_1.pdf]
I wrote VHDL codes for two 32-to-1 MUX, one in normal form of describing the MUX, and the other is using the design method of tree-form of 2-to-1 MUX blocks. I sythesized both codes with TSMC018 library with Design Compiler. Both architectures are behavioral. The base line (non-tree and non-hierarchical)32-to-1 MUX report lower power consumption compared to the tree-form one, which is in contrast with what I've studied for low power design method for MUX. [ref: http://www.cecs.uci.edu/~papers/compendium9403/papers/1997/islped97/pdffiles/t6_1.pdf] Can you please discuss that and tell me what I've done wrong that I get a conflcting results! Thanks
Ok, now I understand whats going on. But without a deep dive into the topic its hard to be able to relate to this topic. Power dissipation is related to used frequency. Maybe the "tree-form" design consumes more dc power but will consume less power on a higher frequency.
Meli wrote: > one in normal form of describing the MUX That results in using a optimized macro from the ASIC supplier. > The base line (non-tree and non-hierarchical)32-to-1 MUX report lower > power consumption compared to the tree-form one, which is in contrast > with what I've studied for low power design method for MUX Lets say it that way: the ASIC supplier has invested several man-years of work in the optimal design of basic elements. It would be highly astonishing when you could find a better solution just from scratch... Meli wrote: > [ref: http://www.cecs.uci.edu/~papers/compendium9403/papers/1997/islped97/pdffiles/t6_1.pdf] result:
1 | The requested URL /~papers/compendium9403/papers/1997/islped97/pdffiles/t6_1.pdf |
2 | was not found on this server. |
Let me give more detail of the results I get. The power report fot base libe MUX is : Cell Internal Power = 3.8167 uW (58%) Net Switching Power = 2.7465 uW (42%) --------- Total Dynamic Power = 6.5631 uW (100%) Cell Leakage Power = 1.2086 nW while the results for tree-form MUX is : Cell Internal Power = 6.9479 uW (64%) Net Switching Power = 3.8347 uW (36%) --------- Total Dynamic Power = 10.7826 uW (100%) Cell Leakage Power = 3.2554 nW Since both architectures are written behaviorally, I supposed DC would optimize both designs the same way. Actually, I'm not forcing it to choose any specific cell, so with the behavioral description, DC will get the mux function and will optimize it the best way it can. One may say, the more general the desgin, DC can apply more optimizations so will result in lower power. If so, then why the tree-form design is proposed to make the design more "low power"? By the way, I attach the paper that I sent the link for.
Now I wanna ask my question in another way. I've designed a 32-to-1 MUX in its general form of description. If I want to extend it to a 256-to-1 MUX, what method should I have in mind to be hopeful that the power result will improve? Isn't the answer the tree-form method of design? Thanks for your time
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