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Forum: FPGA, VHDL & Verilog variable vhdl


von siwar d. (Company: ISIMSfax) (siwardammak)


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good morning
this is my vhdl code
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library ieee  ; 
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use ieee.std_logic_1164.all  ; 
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use ieee.std_logic_arith.all  ;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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use work.genlfsr_pkgg.all;
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-- use work.genlfsr_pkg.all;
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ENTITY composantscrambler  IS 
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  port ( e   : in  std_logic_vector (29 downto 0); 
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         Sel : in  std_logic_vector  (3 downto 0);
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         s   : out std_logic_vector (29 downto 0)
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        );
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END ;
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process (doutGPRS, doutCDMA2000,doutUMTS,doutGSM,doutLTE,doutDVB,doutWCDMA,dout802154g,dout80220, Sel) is
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   begin
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if Sel = "0000" then 
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  s <= doutCDMA2000 ;
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elsif Sel = "0010" then 
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  s <= doutGPRS;
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elsif Sel = "0100" then 
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    s <= doutUMTS;
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elsif Sel = "0110" then 
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    s <= doutGSM;
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elsif Sel = "1000" then 
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    s <= doutLTE;
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elsif Sel = "1010" then 
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    s <= doutDVB;
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elsif Sel = "1100" then 
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    s <= doutWCDMA;
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elsif Sel = "0011" then 
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    s <= dout80216b;
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elsif Sel = "1001" then 
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    s <= doutIS95;
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elsif Sel = "0001" then 
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    s <= doutHSDPA;
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elsif Sel = "1111" then 
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    s <= dout802154g;
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else 
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  s <= dout80220;
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 end if ; 
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 end process;

When I do simulation I got error (** Fatal: (vsim-3420) Array lengths do 
not match. Left is 30 (29 downto 0). Right is 14 (13 downto 0).
#    Time: 0 ns  Iteration: 0  Process: /composantscrambler/line__320 
File: C:/modeltech_10.0c/examples/composant-scrambler.vhd
# Fatal error in Process line__320 at 
C:/modeltech_10.0c/examples/composant-scrambler.vhd line 339) because I 
fixed s to std_logic_vector (29 downto 0) then it take differen value 
(doutIS95 , dout802154g, etc )
So what I can do ?
thanks

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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> I fixed s to std_logic_vector (29 downto 0) then it take differen value
> (doutIS95 , dout802154g, etc )
> So what I can do ?
You can either (1) truncate the long vector or (2) lengthen the 
short one.

In the first case (1) you can assign a default value (others=>'0') to s 
and assign only the relevant bits:
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process (doutGPRS, doutCDMA2000, doutUMTS, doutGSM, doutLTE, doutDVB, doutWCDMA, dout802154g, dout80220, Sel) is
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   begin
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      s <= (others=>'0'); -- default value
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      if    Sel = "0000" then  s(29 downto 29-doutCDMA2000'high) <= doutCDMA2000 ;
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      elsif Sel = "0010" then  s(29 downto 29-doutGPRS'high)     <= doutGPRS; 
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      elsif Sel = "0100" then  s(29 downto 29-doutUMTS'high)     <= doutUMTS;
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      elsif Sel = "0110" then  s(29 downto 29-doutGSM'high)      <= doutGSM;
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      ....
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      else                     s(29 downto 29-dout80220'high)    <= dout80220;
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   end if ;  
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 end process;
This was left aligned.
You can also do it right aligned:
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process (doutGPRS, doutCDMA2000, doutUMTS, doutGSM, doutLTE, doutDVB, doutWCDMA, dout802154g, dout80220, Sel) is
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   begin
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      s <= (others=>'0'); -- default value
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      if    Sel = "0000" then  s(doutCDMA2000'range) <= doutCDMA2000 ;
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      elsif Sel = "0010" then  s(doutGPRS'range)     <= doutGPRS;
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      elsif Sel = "0100" then  s(doutUMTS'range)     <= doutUMTS;
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      elsif Sel = "0110" then  s(doutGSM'range)      <= doutGSM;
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      ....
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      else                     s(dout80220'range)    <= dout80220;
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   end if ;  
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 end process;
Got the idea? Its faily simple, isn't it?


And the second case (2) is already solved :
A few days ago the very same question popped up. Maybe it was asked by 
a classmate of you. He had the error in line 332. Have a look around 
here in the forum. If you try a search for "fatal error" you will find 
the solution: https://embdev.net/topic/302406.

> use ieee.std_logic_arith.all  ;
> use ieee.numeric_std.all;
Who teaches you to use them both together?

> use std.textio.all;
You know that that package is not synthesizeable?

von siwar d. (Company: ISIMSfax) (siwardammak)


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thank you for your attention ,thank you very much

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