Forum: FPGA, VHDL & Verilog vhdl file / package / entity

Author: entity / package (Guest)
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good morning how I can assemble a list of entities in a package ?
how I can point to another file vhdl ?

Author: Lothar Miller (lkmiller) (Moderator)
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Why do you post the same question multiple times?

Pls describe your problem, not how you intend to solve it.
WHY do you want a list of entities in a package?
WHAT do you mean with a "pointer to a VHDL file"?


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