# Forum: FPGA, VHDL & Verilog Design the baud rate synchronizes transmitter and receiver of UART

 Author: momina nisar (Company: uet) (momina) Posted on: 2013-06-10 09:37

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Design the baud rate synchronizes transmitter and receiver of UART.
Clock divider in UART play important role as it provides appropriate
frequency clock as per required by the baud rate. The calculation of
baud rate divider required following formula:
No. of Counts= (FPGA Freq/Baud Rate)/2
Design a module which takes four Baud Rates 600,1200,2400,4800 and
provide the divided clock freq. accordingly.

module ClockDivider(input Clk,output BClk,input [1:0]BSel);
//BClk-Baud Clock
//Clk-input Clock // BSel-Baud Rate Select, 00-600, 01-1200,10-2400,
11-4800
Endmodule

how should i write the verilog code for this....
Please help me

 Author: PittyJ (Guest) Posted on: 2013-06-10 09:52

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Is this your homework?

 Author: Cihan Kalayci (lazoboy61) Posted on: 2013-06-10 09:53

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Look at site 7 in this document:

There is a clock divider example.

Cihan

 Author: Lothar Miller (lkmiller) (Moderator) Posted on: 2013-06-10 09:53

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momina nisar wrote:
> how should i write the verilog code for this....
The firstmost step:
You should have a look how others did similar prescalers.

And then you take that formula and implement a counter which is reloaded
with the appropriate value for the one of the 4 desired frequencies.
About 10 lines of code and you're done...

Cihan Kalayci wrote:
> There is a clock divider example.
Seems to be the wrong HDL...  ;-)

 Author: momina nisar (Company: uet) (momina) Posted on: 2013-06-10 12:22

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No this is not home work i once  read a buk in which it was a question
and now i forget the buk even

• $formula (LaTeX syntax)$