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Forum: FPGA, VHDL & Verilog synthesis of a vhdl code


Author: siwar dammak (Company: ISIMSfax) (siwardammak)
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good morning
please how work synthesis of a vhdl code on modelSim to be configured in 
FPGA ?
thanks on advance

Author: Lothar Miller (lkmiller) (Moderator)
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ModelSim is a simulator.
To synthesize a VHDL description you need a synthesizer. Thats usually 
included in the toolchain of the FPGA supplier...

Author: siwar dammak (Company: ISIMSfax) (siwardammak)
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thanks a lot

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