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Forum: FPGA, VHDL & Verilog error : Cannot drive signal 'e' of mode IN


Author: siwar dammak (Company: ISIMSfax) (siwardammak)
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Good morning
I have an error on my vhdl file, I would affect e to one of my component 
list (scramblerUMTS, scramblerGSM, etc...) when sel is 000 or 0001 
etc...
please I need a reply
tnx

:
Author: Lothar Miller (lkmiller) (Moderator)
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>> "Cannot drive signal 'e' of mode IN" <<
Whats not clear with this error message?
If e is an input you cannot assign a value to it...

> I would affect e to one of my component list
I do not unterstand the problem. e is used nowhere inside the code...

Author: siwar dammak (Company: ISIMSfax) (siwardammak)
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so what the new type of e to will can assibne a value ???

Author: Lothar Miller (lkmiller) (Moderator)
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I'm sorry, I don't have even the faintest idea what your problem is...

You cannot assign a value to e from inside the comp_sc module.
You can assign values to a local signal. Likewise you did with this 
ones:
   SIGNAL data_in_WCDMA : std_logic_vector (24 downto 0);
   SIGNAL scram_en_WCDMA: std_logic;
   SIGNAL scram_rst_WCDMA: std_logic;  
   :
   :

Author: siwar dammak (Company: ISIMSfax) (siwardammak)
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thank you for explaination

it joined a picture of my project implementation, you can help me ?

thank you in advance

Author: Lothar Miller (lkmiller) (Moderator)
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That does not match in width:
e : in std_logic_vector ;

data_in_WCDMA : in std_logic_vector (24 downto 0);
And you cannot assign a unconstrained vector (e) to some other vectors 
with different widths.

As it it not necessary to multiplex the inputs (just think about that 
for half an hour), you must only have an eye on the outputs.
Finally you must input a vector at least the size of the broadest module 
vector (here this is 42 bits) and you must select the interesting 
result to the output.
LIBRARY ieee  ; 
USE ieee.std_logic_1164.all  ; 
USE ieee.std_logic_arith.all  ; 
ENTITY comp_sc  IS 
  port ( e   : in  std_logic_vector (41 downto 0); 
         Sel : in  std_logic_vector  (2 downto 0);
         s   : out std_logic_vector (41 downto 0)
        );
END ;
ARCHITECTURE arch_comp_sc OF comp_sc IS
  : 
  :
  SIGNAL data_in_GPRS : std_logic_vector (6 downto 0); -- the smallest
  SIGNAL data_out_GPRS : std_logic_vector (6 downto 0);
  :
  :  
  SIGNAL data_in_CDMA2000 : std_logic_vector (41 downto 0); -- the broadest
  SIGNAL data_out_CDMA2000 : std_logic_vector (41 downto 0);
  : 
  :
BEGIN 
   data_in_CDMA2000 <= e;
   data_in_GPRS     <= e(6 downto 0);
   :
   :
   process (data_out_GPR, data_out_CDMA2000, Sel) is
   begin
      s <= (others => '0'); -- assign a default value to unused output bits
      case Sel is
         when "000"  => s <= data_out_CDMA2000;
         when "001"  => s <= data_out_GPRS;
         when "010"  => ...
         when "011"  => ...
         :
      end case;
   end process;
   :


BTW: you did some simple&stupid copy&paste work without thinking. How 
much clocks do you have? Ho much resets and enables? Where do the come 
from?

Author: siwar dammak (Company: ISIMSfax) (siwardammak)
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thank you a lot :)
 I have 1 clk and 2 resets (scram_rst_WCDMA,rst_WCDMA) in every 
component

Author: siwar dammak (Company: ISIMSfax) (siwardammak)
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good morning
please can you tell me what is the name of this step in vhdl 
programmation ?

Author: donDude (Guest)
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in which step?

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