Hi guys, I need some help in simply (for people who know vhdl quite
well) project of processor. Below I put project assumptions, some of
them are already done, but highly possible that are wrong wrote in vhdl.
Please, any kind of help I will never do it myself.
Processor project:
Data bus and address bus are 16 bits.
1) List of commands:
* MOV arg1, arg2 - shift arg2 in arg1 (arg1 - register, arg2 - address
or register)
* ADD arg, arg2 - addition arg2 to arg1, result in arg1 (arg1 -
register, arg2 - address or register)
* SUB arg, arg2 - substraction arg2 from arg1 result in arg1 (arg1 -
register, arg2 - address or register)
* BINtoBCD arg1 (conversion value binary into BCD, result in arg1)
* RDCTRL arg1 (load register marker to arg1 - register or address in
memory)
* WRCTRL arg1 (record register marker from arg1 - register or address in
memory)
* ASHL arg1, arg2 (arithmetic shift into left of value in arg1 of
arg2-bits; arg1 -register, arg2 - register or constant 3-bit, result in
arg1)
* ASHR arg1, arg2 (arithmetic shift into right of value in arg1 of
arg2-bits; arg1 -register, arg2 - register or constant 3-bit, result in
arg1)
IF it is needed, set markers C,Z,S,P.
2)Records (registers)
* ES - register of segment (16 bit register stores the address of the
block)
* AP1, AP2 - registers address 8 bit for stores address of shift)
3)System of cooperation with memory - way of segmentation
Range segments: 9 bits
Range shifts: 7 bits
I attached files with clear code were received from leader from my
univesity - everything was done in Quartus12.
I noticed here many people well know vhdl, and I guess for you it's few
minutes. IF someone could look at code, would be great.
Many thanks in advance.
And below I also attached what is done (but probably wrong - many errors
while trying to compile code)
ALU:
1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.numeric_std.all;
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4 |
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5 | entity ALU is
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6 | port ( A : in signed(15 downto 0);
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7 | B : in signed(15 downto 0);
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8 | Salu : in bit_vector (3 downto 0);
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9 | LDF : in bit;
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10 | clk : in bit;
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11 | Y : out signed (15 downto 0);
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12 | C,Z,S : inout std_logic
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13 |
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14 | );
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15 | end entity;
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16 |
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17 | function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is
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18 | variable i : integer:=0;
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19 | variable bcd : std_logic_vector(11 downto 0) := (others => '0');
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20 | variable bint : std_logic_vector(7 downto 0) := bin;
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21 |
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22 | begin
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23 | for i in 0 to 7 loop -- repeating 8 times.
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24 | bcd(11 downto 1) := bcd(10 downto 0); --shifting the bits.
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25 | bcd(0) := bint(7);
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26 | bint(7 downto 1) := bint(6 downto 0);
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27 | bint(0) :='0';
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28 |
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29 |
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30 | if(i < 7 and bcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
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31 | bcd(3 downto 0) := bcd(3 downto 0) + "0011";
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32 | end if;
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33 |
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34 | if(i < 7 and bcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
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35 | bcd(7 downto 4) := bcd(7 downto 4) + "0011";
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36 | end if;
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37 |
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38 | if(i < 7 and bcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
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39 | bcd(11 downto 8) := bcd(11 downto 8) + "0011";
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40 | end if;
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41 |
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42 |
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43 | end loop;
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44 | return bcd;
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45 | end to_bcd;
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46 |
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47 |
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48 | architecture rtl of ALU is
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49 | begin
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50 | process (Salu, A, B, clk)
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51 | variable res, AA, BB,CC: signed (16 downto 0);
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52 | variable CF,ZF,SF : std_logic;
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53 | begin
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54 | AA(16) := A(15);
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55 | AA(15 downto 0) := A;
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56 | BB(16) := B(15);
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57 | BB(15 downto 0) := B;
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58 | CC(0) := CF;
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59 | CC(16 downto 1) := "0000000000000000";
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60 | case Salu is
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61 | when "0000" => res := AA; -- mov
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62 | when "0010" => res := AA + BB; --add
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63 | when "0011" => res := AA - BB; --sub
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64 | when "0001" => res := to_bcd(AA); -- BINtoBCD
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65 |
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66 | when "1111" => res(16) := AA(16);
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67 | res(15 downto 0) := AA(16 downto 1); --shift (wrong!)
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68 | end case;
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69 | Y <= res(15 downto 0);
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70 | Z <= ZF;
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71 | S <= SF;
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72 | C <= CF;
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73 | if (clk'event and clk='1') then
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74 | if (LDF='1') then
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75 | if (res = "00000000000000000") then ZF:='1';
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76 | else ZF:='0';
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77 | end if;
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78 | if (res(15)='1') then SF:='1';
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79 | else SF:='0'; end if;
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80 | CF := res(16) xor res(15);
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81 | end if;
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82 | end if;
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83 | end process;
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84 | end rtl;
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