Forum: FPGA, VHDL & Verilog Verilog Input Syntax

Author: Emre Ergecen (Guest)
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Hi everyone,

Is it possible to define such inputs and outputs?

module Minimize(reg_inp, reg_out);

  input [3:0] reg_inp[0:255];
  output [3:0] reg_out[0:255];

  reg [3:0] reg_inp[0:255];
  reg [3:0] reg_out[0:255];


Author: Lattice User (Guest)
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Verilog 2001: No
SystemVerilog: Yes (not sure about the syntax)


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