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Forum: FPGA, VHDL & Verilog Verilog VGA code HS VS timing


Author: Keny Joneyer (Guest)
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Hi everyone,

I have a basys2 digilent fpga card. I just want to draw a picture on the 
screen with VGA cable. The following is the code that I wrote. However, 
it is not working that I expect. Could you please help me about where 
the problem is? Thanks ..


`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//////////
// Company:
// Engineer:
//
// Create Date:    15:41:47 05/18/2013
// Design Name:
// Module Name:    kodilk
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////
//////////
module basla(clr,clk,hsync,vsync,red,green,blue);


  input wire clr;
  input wire clk; // This is for 50Mhz clock signal . Connect B8 pin
  output wire hsync;    //horizontal sync out
  output wire vsync;    //vertical sync out
  output reg [2:0] red;  //red vga output
  output reg [2:0] green; //green vga output
  output reg [1:0] blue;  //blue vga output

  // This block is reponsible of 25 Mhz clock generation.
  reg clk_pixel=0;
  always @ (posedge clk)
  begin

    clk_pixel <= ~clk_pixel ;  // clk_pixel is equal to 50/2=25 Mhz.

  end
  // Counting mechanism
  reg [9:0] hc;
  reg [9:0] vc;

  always @(posedge clk_pixel or posedge clr)


  begin
  if (clr == 1)
  begin
    hc <= 0;
    vc <= 0;
  end
  else
  begin
    if (hc < 799)
      hc <= hc + 1;
    else
    begin
      hc <= 0;
      if (vc < 524)
        vc <= vc + 1;
      else
        vc <= 0;
    end
  end
end



  // end of counting mechanism

  //sync pulses - active low-

  assign hsync = (hc < 96) ? 0:1;
  assign vsync = (vc < 2) ? 0:1;

  // lets draw some picture
    always @ (hc or vc)
    begin
      if (vc >34 && vc < 515)
      begin
      if (hc > 143 && hc < 700)
        begin
        red = 3'b111;
        green = 3'b000;
        blue= 2'b00;
        end

    end
    end

endmodule






Plus , ucf file:

CE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "blue[0]"  LOC = "H13"  ;
NET "blue[1]"  LOC = "J13"  ;
NET "clk"  LOC = "B8"  ;
NET "clr"  LOC = "N3"  ;
NET "green[0]"  LOC = "F14"  ;
NET "green[1]"  LOC = "G13"  ;
NET "green[2]"  LOC = "G14"  ;
NET "hsync"  LOC = "J14"  ;
NET "red[0]"  LOC = "C14"  ;
NET "red[1]"  LOC = "D13"  ;
NET "red[2]"  LOC = "F13"  ;
NET "vsync"  LOC = "K13"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

Author: Lothar Miller (lkmiller) (Moderator)
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> However, it is not working that I expect.
How did you find that out?
What do you expect?
And how is "the code" working?
Do you have a testbench for this code?

Author: bko (Guest)
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I can see two clocks in your code, it may not be the problem,..
> always @ (posedge clk)
>  begin
>    clk_pixel <= ~clk_pixel ;  // clk_pixel is equal to 50/2=25 Mhz.

>always @(posedge clk_pixel or posedge clr)

.. but its better to use only one clock, for example:
 always @ (posedge clk)
  begin
    clk_pixe_en <= ~clk_pixel_en ;  // clk_pixel is equal to 50/2=25 Mhz.
    if (clk_pixe_en)
       begin
       // do something
       if (clr == 1)
       begin
          hc <= 0;
          vc <= 0
       // and so on

and here you create a logic loop or a latch, use a "else" for each "if"
to avoid that:
>// lets draw some picture
>    always @ (hc or vc)
>    begin
>      if (vc >34 && vc < 515)
>      begin
>      if (hc > 143 && hc < 700)
>        begin
>        red = 3'b111;
>        green = 3'b000;
>        blue= 2'b00;
>        end
      else
         red = ... 
   else
     red =

Author: vaishali (Guest)
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sir
i have verilog code for vga controler for fpga basys2. But i dont know 
how to use it. I maen how to run it without fpga. can we show ant output 
signal which will show mw my code is working properly.

please answer me asap.
thank you

Author: Lothar Miller (lkmiller) (Moderator)
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vaishali wrote:
> sir i have verilog code for vga controler
Pls start a NEW thread for a NEW problem!

> I maen how to run it without fpga.
You want to simulate it? Then you need a testbench for that module. 
Or at least a clock...

What toolchain/simulator do you use?

Author: vaishali (Guest)
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i dont have test bench. I am using Xilinx software

Author: Vaishali Masal (vaishali18)
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vaishali wrote:
> i dont have test bench. I am using Xilinx software.Can u provide me test bench 
for it

Author: Lothar Miller (lkmiller) (Moderator)
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Vaishali M. wrote:
> Can u provide me test bench for it
Isn't that your homework?
So lets try it that way: you start with something, and when you 
encounter specific problems, then you ask and hopefully someone gives 
you some help. But first it is your job. No one is intended to do your 
homework for free...

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