Hi All, I am dealing with the pin assignments specifications for Altera's Cyclone IV FPGA. I am using Altera's Quartus II software and using its QSYS tool I have designed a system to interface DDR2 SDRAM with FPGA. While I was assigning pin assignments to FPGA. I came across the feature - On-chip termination, which fascinated me as it can deduct the requirement of adding pull-up resistors and can reduce the bulkiness of the board. As all the pins from FPGA to SDRAM are output or bi-directional, I have applied output termination with series 50 ohms with calibration to all the pins. My questions are- 1.Is my attempt of applying output termination, with series 50 ohms calibration, to bi-directional pins correct? (I have read that For input pins, input termination should be used with parallel resistors For output pins output termination should be used with series resistors For bi-directional both the input and output termination or dynamic termination should be used. But in Cyclone IV input termination and dynamic termination options are not available. These options are there in Stratix family FPGAs) 2. If output termination with series 5o ohm with calibration is correct, do I need to add any external resistors for termination on FPGA side?(Except RUP and RDN resistors) Ashish Devre
at first we should distinguish on chip termination for both FPGA and DDR2 chip, secondly oct does not necessarily eliminate the demand of external termination in all cases. designing a ddr2/ddr3 interface requires attention at all parts of the design like ddr2 chip (number, position), fpga (oct options, si issues) and board design so different methods of termination can be applied according to the particular demands before answering some of your particular questions seriously, some additional requirements should be provided general information about handling of ddr issues can be taken from several sources of the inet like e.g. the ddr designers guide from micron, also altera and xilinx have ddr integration apps available
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