Forum: FPGA, VHDL & Verilog calling module in verilog

Author: Mina Magdy (Company: N/A) (mina)
Posted on:

Rate this post
0 useful
not useful
 i have a problem in calling module in verilog that when i call a module 
that make alot of calculation( module calc) it gives me the o/p delayed 
a clock
 and also another module for ram and module for rom thats also delay one 
clock so when i take the delayed o/p from the (module calc) and but it 
in the (module RAM) it put the values at wrong places in the ram.

 module calc is consists of a module for lookuptable(module LUT) and 
another module for adding and subtract floating point(module addsub).

 i need a form of module that doesn't delay (what could make a delay in 
a module to avoid) because my system is consists of alot of modules in 
side each other.

 please help me if you can or if you have any suggestion.

Author: Ale (Guest)
Posted on:

Rate this post
0 useful
not useful
Well, you are rather vague on how the modules operate... you seem to 
want combinatorial results and you get clocked results. That seems to 
lead to timing problems. I'd suggest you get GTKWave, for instance, and 
analyze those vcd files in detail to see when the data arrive and when 
it is supposed to arrived.
A better/detailed explanation of what you have may also help...


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.