I am designing and LFSR based pseudo code generator.. but the final 
output is coming as unknown.. can anybody help me to rectify this issue. 
I have attached the circuit diagram, code & output wave form. In the 
circuit before each FF i have added an Mux..


Code
========================

ENTITY watermark_gen IS
   PORT(
      clk     : IN     std_logic;
      start   : IN     std_logic;
      key     : in     std_logic_vector (7 downto 0);
      wm_data : OUT    std_logic_vector (1 DOWNTO 0)
   );

-- Declarations

END ENTITY watermark_gen ;

--
ARCHITECTURE struct OF watermark_gen IS
component D_ff is
 port( d,clock,enable : in std_logic;
        q,qbar        : out std_logic);
end component;

component nor1 is
   port ( x,y : in std_logic;
            z : out std_logic);
end component;

component or3 is
  port (w,x,y : in std_logic;
            z : out std_logic);
end component;

component or4 is
  port ( v,w,x,y : in std_logic;
               z : out std_logic);
end component;

component mux1 is
port (  x: in std_logic;
      y: in std_logic;
        c: in std_logic;
        z: out std_logic);
end component;

component xor1 is
  port (x,y : in std_logic;
          z : out std_logic);
end component;

signal temp : std_logic_vector(0 to 15):= "0000000000000000";
signal mx_tmp: std_logic_vector(0 to 8):="000000000";
signal mx_zero: std_logic := '0';
signal mx_sel: std_logic := '0';

BEGIN
  temp(7) <= key(7);
  temp(6) <= key(6);
  temp(5) <= key(5);
  temp(4) <= key(4);
  temp(3) <= key(3);
  temp(2) <= key(2);
  temp(1) <= key(1);
  temp(0) <= key(0);
  p1: mux1 port map ( temp(7),mx_zero,mx_sel,mx_tmp(0));
  p2: D_ff port map ( mx_tmp(0),clk,start,temp(6),open);
  p3: mux1 port map ( temp(6),mx_zero,mx_sel,mx_tmp(1));
  p4: D_ff port map ( mx_tmp(1),clk,start,temp(8),open);
  p5: xor1 port map ( temp(7),temp(8),temp(5));
  p6: mux1 port map ( temp(5),mx_zero,mx_sel,mx_tmp(2));
  p7: D_ff port map ( mx_tmp(2),clk,start,temp(9),open);
  p8: xor1 port map ( temp(7),temp(9),temp(4));
  p9: mux1 port map ( temp(4),mx_zero,mx_sel,mx_tmp(3));
  p10: D_ff port map ( mx_tmp(3),clk,start,temp(10),open);
  p11: xor1 port map ( temp(7),temp(10),temp(3));
  p12: mux1 port map ( temp(3),mx_zero,mx_sel,mx_tmp(4));
  p13: D_ff port map ( mx_tmp(4),clk,start,temp(2),open);
  p14: mux1 port map ( temp(2),mx_zero,mx_sel,mx_tmp(5));
  p15: D_ff port map ( mx_tmp(5),clk,start,temp(1),open);
  p16: mux1 port map ( temp(1),mx_zero,mx_sel,mx_tmp(6));
  p17: D_ff port map ( mx_tmp(6),clk,start,temp(0),open);
  p18: mux1 port map ( temp(0),mx_zero,mx_sel,mx_tmp(7));
  p19: D_ff port map ( mx_tmp(7),clk,start,temp(11),open);
  p20: or3 port map ( mx_tmp(1),mx_tmp(2),mx_tmp(3),temp(12));
  p21: or4 port map ( mx_tmp(4),mx_tmp(5),mx_tmp(6),mx_tmp(7),temp(13));
  p22: nor1 port map ( temp(12),temp(13),temp(14));
  p23: xor1 port map ( temp(11),temp(14),temp(15));
  wm_data(0) <= mx_tmp(1);
  wm_data(1) <= mx_tmp(1) xor mx_tmp(2);

END ARCHITECTURE struct;