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Forum: FPGA, VHDL & Verilog errors I can't find ansrews for


Author: Martin Potts (Guest)
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Why am I getting the erros at the end Process and end architecture?
Thanks
Martin

Author: cfgardiner (Guest)
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For one thing,

these lines should be 'end if' and not 'endif'

        if in_1 = '1' then out_1 <= '1' after 2ns ;
        endif;

        if in_1 = '0' then out_1 <= '0' after 2ns ;
        endif;

        if in_2 = '1' then out_2 <= '1' after 2ns ;
        endif;

Author: Lothar Miller (lkmiller) (Moderator)
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And also in VHDL every process must have a sensitivity list or a wait 
statement inside. The process in question doesn't have any of them...

I strongly recommend to take any book about VHDL and have a look for 
the keyword /loop/:
   loop
 ...
   end loop;

That book about VHDL will also help you with the next steps. As an 
alternative you can use Google and have a look how others are doing 
VHDL...

Author: Martin Potts (Guest)
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Thanks
That solved the first problem.
Still have the other problem, is it because I used basic in 
architecture?

I am using "The Designer's Guide to VHDL" second edition by Peter J. 
Ashenden
The templet came from page 14.
I am using Altera Max V Quartus II.
Just trying to understand to process from design to program.
Martin

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