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Forum: FPGA, VHDL & Verilog VHDL Synthesis


Author: Vibhuti R. (vibhuti_r)
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I have written 2 state machines in my VHDL code. The simulation works 
fine, but the code does not synthesize. Any help would be appreciated. 
Here is my code:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_arith.ALL;
    use IEEE.STD_LOGIC_unsigned.ALL;
    use IEEE.NUMERIC_STD.ALL;

    entity pulse_width is
    Port (  clk : in STD_LOGIC;
          timer2:in std_logic;
          input: in STD_LOGIC;
          result: inout STD_LOGIC_VECTOR (15 downto 0);
          SEL_LINE: IN STD_LOGIC_VECTOR(5 DOWNTO 0);
          data_out: out STD_LOGIC_VECTOR (23 downto 0):=x"000000");
    end pulse_width;

    architecture Behavioral of pulse_width is
      TYPE count_states is (s0,s0_dash,s1,s2,s3,s1_dash);
      SIGNAL current_state, next_state : count_states := s0 ;
      TYPE write_states is (ws0,ws0_dash,ws1,ws2,ws3,ws4);
      SIGNAL current_state1, next_state1 : write_states := ws0 ;
      TYPE index_array is ARRAY(integer range 0 to 65535) of 
std_logic_vector(15 downto 0);
      SIGNAL mem: index_array;
      SIGNAL count: std_logic_vector(15 downto 0):=x"0000";
      SHARED VARIABLE j: integer:=0;
      SHARED VARIABLE a,i: integer:=1;
      SIGNAL 
flag,push_data,push_first,push_final,push_pulses,rw_first,rw_end: 
std_logic:='0';
      SIGNAL y_clk_input ,y_clk_timer2, enable_count: std_logic:='0';
      SIGNAL first,final: std_logic_vector(15 downto 0):= x"0001";

    begin
    -- Pulse width count

    process (clk)
    begin
      if rising_edge(clk) then
        current_state<=next_state;
        current_state1<=next_state1;
      end if;
    end process;


    process(input,SEL_LINE,current_state)
    begin

    ------------------------------------------------------------------------
      case current_state is
      when s0 =>
        if(input='1') then
          next_state<=s1;
        else
          next_state<=s0;
        end if;
      when s1 =>
        flag<='0';
        if input='1' then
          count <= count+ x"0001";
          next_state<=s1_dash;
        else
          next_state<=s2;
        end if;
      when s1_dash =>
        if input='1' then
          count <= count+ x"0001";
          next_state<=s1;
        else
          next_state<=s2;
        end if;
      when s2 =>
          result <= count;
          next_state<=s3;
      when s3=>
          count <= x"0000";
          next_state<=s0;
          enable_count<='0';
      when others =>
        next_state<=s0;
      end case;

    ------------------------------------------------------------------------ 
--
      case current_state1 is
      when ws0 =>
        if  (result>x"0000") then
        next_state1<=ws1;
        else
        next_state1<=ws0_dash;
        end if;
      when ws0_dash =>
        if  (result>x"0000") then
        next_state1<=ws1;
        else
        next_state1<=ws0;
        end if;
      when ws1=>
        if rw_first='1' and rw_end='1' then
        next_state1<=ws0;
        else
          mem(a) <= result;
          a:=a+1;
          final<=final+x"0001";
          next_state1<=ws2;
        end if;
      when ws2 =>
          next_state1<=ws0;
          result<=x"0000";
      when others  =>
        next_state1<=ws0;
      end case;
    end process;
I eventually need to implement three state machines.

Author: Duke Scarring (Guest)
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> The simulation works fine, but the code does not synthesize.
What is the error message?

Duke

Author: Vibhuti R. (vibhuti_r)
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Duke Scarring wrote:
>> The simulation works fine, but the code does not synthesize.
> What is the error message?
>
> Duke

Hi Duke,

I am using Xilinx 13.2. The code gets stuck in the synthesis part and 
does not complete the process. Hence no error message is visible.

Author: Lothar Miller (lkmiller) (Moderator)
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> but the code does not synthesize.
Is it the synthesizer that stucks or is it one of the later steps?
Which target (Virtex, Spartan)? And which FPGA size?

> I am using Xilinx 13.2.
Try the new parser:
http://www.lothar-miller.de/s9y/archives/79-use_ne...

    use IEEE.STD_LOGIC_arith.ALL;
    use IEEE.STD_LOGIC_unsigned.ALL;
    use IEEE.NUMERIC_STD.ALL;
Where did you see this?
Do never ever use them three together!
Otherwise you will have curious effects due to double definitions of 
types and arithmetics.

> I eventually need to implement three state machines.
Why all of them in 1 process?

    process(input,SEL_LINE,current_state)
    begin
      :
      when s2 =>
          result <= count;
Your simulation is wrong because to count is missing in the 
sensitivity list.

      TYPE index_array is ARRAY(integer range 0 to 65535) of std_logic_vector(15 downto 0);
Does your FPGA have that much RAM?

      SHARED VARIABLE j: integer:=0;
      SHARED VARIABLE a,i: integer:=1;
Are you sure you need those?
And: never use unconstrained integers.

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