Forum: FPGA, VHDL & Verilog doubt on how to connect the ports in vhdl

Author: Elaine San (Company: estudy) (elainen)
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I'm doing a vhdl code and need to connect the input directly at the 
exit, as I do this? Always connect the main exit at the exit doors ands, 
ors, etc..

Author: Lothar Miller (lkmiller) (Moderator)
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Take ANY book about VHDL synthesis and look on the very first pages...
library IEEE;

entity InToOut is
    Port ( output : out STD_LOGIC;
           input  : in  STD_LOGIC);
end InToOut;

architecture Behavioral of InToOut is

  output <= input;

end Behavioral; 


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