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Forum: FPGA, VHDL & Verilog doubt on how to connect the ports in vhdl


doubt on how to connect the ports in vhdl
von Elaine S. (Company: estudy) (elainen)

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I'm doing a vhdl code and need to connect the input directly at the 
exit, as I do this? Always connect the main exit at the exit doors ands, 
ors, etc..

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Re: doubt on how to connect the ports in vhdl
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Take ANY book about VHDL synthesis and look on the very first pages...

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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entity InToOut is

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    Port ( output : out STD_LOGIC;

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           input  : in  STD_LOGIC);

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end InToOut;

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architecture Behavioral of InToOut is

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begin

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  output <= input;

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end Behavioral;


  


  




  

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