EmbDev.net

Forum: FPGA, VHDL & Verilog 8-Bit ALU Model using VHDL


Author: John Clark (Guest)
Posted on:

Rate this post
1 useful
not useful
Hey everyone,

It has been a while since I programmed using VHDL, plus I don't have 
much experience. I am trying to create a simple, structural, 8-bit ALU 
model that is capable of doing two's complement arithmetic (addition and 
subtraction) and that can do the logic functions NAND and NOR.

I started out creating an Add_Sub and Mux in the megawizard. After that, 
I am pretty much lost. I believe it's something like having a top-level 
entity that comprises the components and lays out the basic 
architecture.

If anyone can point me in the right direction, or what I'm missing, it 
would be greatly appreciated.

ADD_SUB Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY lpm;
USE lpm.all;

ENTITY Add_Sub IS
  PORT
  (
    add_sub  : IN STD_LOGIC ;
    cin      : IN STD_LOGIC ;
    dataa    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    datab    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    cout     : OUT STD_LOGIC ;
    overflow : OUT STD_LOGIC ;
    result   : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
  );
END Add_Sub;


ARCHITECTURE SYN OF add_sub IS

  SIGNAL sub_wire0  : STD_LOGIC ;
  SIGNAL sub_wire1  : STD_LOGIC ;
  SIGNAL sub_wire2  : STD_LOGIC_VECTOR (7 DOWNTO 0);



  COMPONENT lpm_add_sub
  GENERIC (
    lpm_direction       : STRING;
    lpm_hint            : STRING;
    lpm_representation  : STRING;
    lpm_type            : STRING;
    lpm_width           : NATURAL
  );
  PORT (
      add_sub  : IN STD_LOGIC ;
      cin      : IN STD_LOGIC ;
      datab    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
      overflow : OUT STD_LOGIC ;
      cout     : OUT STD_LOGIC ;
      dataa    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
      result   : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
  );
  END COMPONENT;

BEGIN
  overflow <= sub_wire0;
  cout     <= sub_wire1;
  result   <= sub_wire2(7 DOWNTO 0);

  LPM_ADD_SUB_component : LPM_ADD_SUB
  GENERIC MAP (
    lpm_direction      => "UNUSED",
    lpm_hint           => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",
    lpm_representation => "SIGNED",
    lpm_type           => "LPM_ADD_SUB",
    lpm_width          => 8
  )
  PORT MAP (
    add_sub  => add_sub,
    cin      => cin,
    datab    => datab,
    dataa    => dataa,
    overflow => sub_wire0,
    cout     => sub_wire1,
    result   => sub_wire2
  );



END SYN;


MUX Code:
 LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY MUX2X8 IS
  PORT
  (
    data0x  : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    data1x  : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    sel     : IN STD_LOGIC ;
    result  : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
  );
END MUX2X8;


ARCHITECTURE SYN OF mux2x8 IS

--  type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;

  SIGNAL sub_wire0  : STD_LOGIC_VECTOR (7 DOWNTO 0);
  SIGNAL sub_wire1  : STD_LOGIC_VECTOR (7 DOWNTO 0);
  SIGNAL sub_wire2  : STD_LOGIC_2D (1 DOWNTO 0, 7 DOWNTO 0);
  SIGNAL sub_wire3  : STD_LOGIC_VECTOR (7 DOWNTO 0);
  SIGNAL sub_wire4  : STD_LOGIC ;
  SIGNAL sub_wire5  : STD_LOGIC_VECTOR (0 DOWNTO 0);

BEGIN
  sub_wire3          <= data0x(7 DOWNTO 0);
  result             <= sub_wire0(7 DOWNTO 0);
  sub_wire1          <= data1x(7 DOWNTO 0);
  sub_wire2(1, 0)    <= sub_wire1(0);
  sub_wire2(1, 1)    <= sub_wire1(1);
  sub_wire2(1, 2)    <= sub_wire1(2);
  sub_wire2(1, 3)    <= sub_wire1(3);
  sub_wire2(1, 4)    <= sub_wire1(4);
  sub_wire2(1, 5)    <= sub_wire1(5);
  sub_wire2(1, 6)    <= sub_wire1(6);
  sub_wire2(1, 7)    <= sub_wire1(7);
  sub_wire2(0, 0)    <= sub_wire3(0);
  sub_wire2(0, 1)    <= sub_wire3(1);
  sub_wire2(0, 2)    <= sub_wire3(2);
  sub_wire2(0, 3)    <= sub_wire3(3);
  sub_wire2(0, 4)    <= sub_wire3(4);
  sub_wire2(0, 5)    <= sub_wire3(5);
  sub_wire2(0, 6)    <= sub_wire3(6);
  sub_wire2(0, 7)    <= sub_wire3(7);
  sub_wire4          <= sel;
  sub_wire5(0)       <= sub_wire4;

  LPM_MUX_component : LPM_MUX
  GENERIC MAP (
    lpm_size   => 2,
    lpm_type   => "LPM_MUX",
    lpm_width  => 8,
    lpm_widths => 1
  )
  PORT MAP (
    data   => sub_wire2,
    sel    => sub_wire5,
    result => sub_wire0
  );



END SYN;

Author: Schlumpf (Guest)
Posted on:

Rate this post
0 useful
not useful
It´s something like:
"I am not experienced in cars but I bought a tyre and a camshaft and I 
want to build a car. Can anybody point me in the right direction?"

Author: John Clark (Guest)
Posted on:

Rate this post
0 useful
not useful
*Tire

Dude, don't be an idiot. And by the way, I'm sure if someone wanted to 
know how to build a car, there would be someone intelligent enough to 
tell a person how. If you're not, then just stay out of the 
conversation.

People learn by example, by mistakes, or by instructions. In this case, 
I'm trying to learn by instruction. All I asked for was some help, so 
next time use a little introspection before you cast arrogant remarks in 
an open forum.

Author: Martin (Guest)
Posted on:

Rate this post
0 useful
not useful
Why  don't  you  simply  say

if(command) c=a+b ; else  c=a-b;

?

Nobody pays  you  for doing digital
design  on gate level.

Author: Schlumpf (Guest)
Posted on:

Rate this post
0 useful
not useful
Dude, don´t be an idiot!

what you posted is only a small fragmet of what is needed for an alu.
And now you ask the people to help you to make an alu out of this.
I just wanted to show the really bad quality of your question. But 
probably you didn´t undertood this.
If you ask a proper question you´ll get a proper answer!

I think you have no glue of what you´re doing here.
But you want to learn things by instruction. So why don´t you start with 
something more easy. You don´t know what a top level is and you don´t 
know how to connect certain componentes. So start with a small example. 
E.g. two AND-Gates.

Words you can google are:
COMPONENT, PORT MAP, etc..

If you are familiar with this than you can try to make a project. And if 
you stuck then, you are able to ask sensible questions.

Anyway, maybe you find a teacher here giving you a general VHDL-course.

btw. I wonder why you don´t use Verilog. Because if you write "tire" you 
must be from cotton-picker-country, where Verilog is the HDL that 
"rocks" :-)

Author: Schlumpf (Guest)
Posted on:

Rate this post
0 useful
not useful
>>Why  don't  you  simply  say
>>if(command) c=a+b ; else  c=a-b;

maybe because Megawizard doesn´t have a click-and-ready solution for 
this statement ;-)

A simple ALU may be "described" like this (you don´t "program" with 
VHDL)

case COMMAND is
  when "00" => C <= A + B;
  when "01" => C <= A - B;
  when "10" => C <= not (A and B);
  when "11" => C <= not (A or B);
  when others => NULL;
end case;

I hope this helps you.

Author: chris (Guest)
Posted on:

Rate this post
0 useful
not useful
Ha John you must be in Eisenbarth's class too.

I'm working with the same prompt.

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
> Ha John you must be in Eisenbarth's class too.
Looks like he is. Greeting to Texas from Germany... ;-)

@ John
Are you are allowed to use third party cores in your homework? Do you 
have to do the (really senseless) job and just wire some components 
together? Aren't you allowed to use behavioral description (like all the 
others around the wordl)?

A mux is a fairly simple design, even in a structural description you 
should be allowed to use this:
ENTITY MUX2X8 IS
  PORT (
    data0x  : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    data1x  : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    sel     : IN STD_LOGIC ;
    result  : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
  );
END MUX2X8;

ARCHITECTURE SYN OF mux2x8 IS
BEGIN
  result  <= data0x when sel='1' else data0x;
END SYN;
The "upper level wiring" then can be done structural (even if that makes 
no further sense to me...).

Author: Klaus (Guest)
Posted on:

Rate this post
0 useful
not useful
it have been difficult times, when we all did our homework on our own...

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.