am new in vhdl really confused on how to start the vhdl code for this architecture architecture attached. will be glad with any response thanks
It's a SPI master and quite similar to this implementation: http://www.lothar-miller.de/s9y/categories/45-SPI-Master In your case it's unclear where the clock shall came from. Are you allowed to use an input clock to generate the SPI Clock?
The clock is generated by the master device through Mosi and Miso Thanks for the link. had a look at it but couldnt understand the comments as it not written in english
> had a look at it but couldnt understand the comments > as it not written in english You don't need to understand the comments if you understand the VHDL code itself... Of course it doesn't help if you say "I don't understand it!" What is particular unclear? Did you at least do the simulation on your own?
i did the simulation using altium designer the test bench i got wasnt working generated a new test bench and used the same stimulus ------------------------------------------------------------------------ -- ------------------------------------------------------------ -- VHDL Testbench for spi_master -- 2013 2 25 22 8 52 -- Created by "EditVHDL" -- "Copyright (c) 2002 Altium Limited" ------------------------------------------------------------ Library IEEE; Use IEEE.std_logic_1164.all; Use IEEE.std_logic_textio.all; Use STD.textio.all; ------------------------------------------------------------ ------------------------------------------------------------ entity Testspi_master is end Testspi_master; ------------------------------------------------------------ ------------------------------------------------------------ architecture stimulus of Testspi_master is file RESULTS: TEXT open WRITE_MODE is "results.txt"; procedure WRITE_RESULTS( clk: std_logic; MISO: std_logic; MOSI: std_logic; RX_Data: std_logic_vector(7 downto 0); SCLK: std_logic; SS: std_logic; TX_Data: std_logic_vector(7 downto 0); TX_Done: std_logic; TX_Start: std_logic ) is variable l_out : line; begin write(l_out, now, right, 15); write(l_out, clk, right, 2); write(l_out, MISO, right, 2); write(l_out, MOSI, right, 2); write(l_out, RX_Data, right, 9); write(l_out, SCLK, right, 2); write(l_out, SS, right, 2); write(l_out, TX_Data, right, 9); write(l_out, TX_Done, right, 2); write(l_out, TX_Start, right, 2); writeline(RESULTS, l_out); end procedure; component spi_master port ( clk: in std_logic; MISO: in std_logic; MOSI: out std_logic; RX_Data: out std_logic_vector(7 downto 0); SCLK: out std_logic; SS: out std_logic; TX_Data: in std_logic_vector(7 downto 0); TX_Done: out std_logic; TX_Start: in std_logic ); end component; signal clk: std_logic; signal MISO: std_logic; signal MOSI: std_logic; signal RX_Data: std_logic_vector(7 downto 0); signal SCLK: std_logic; signal SS: std_logic; signal TX_Data: std_logic_vector(7 downto 0); signal TX_Done: std_logic; signal TX_Start: std_logic; begin DUT:spi_master port map ( clk => clk, MISO => MISO, MOSI => MOSI, RX_Data => RX_Data, SCLK => SCLK, SS => SS, TX_Data => TX_Data, TX_Done => TX_Done, TX_Start => TX_Start ); STIMULUS0:process begin -- insert stimulus here wait; end process; WRITE_RESULTS( clk, MISO, MOSI, RX_Data, SCLK, SS, TX_Data, TX_Done, TX_Start ); end architecture; ------------------------------------------------------------ ------------------------------------------------------------ after the simulation no data showed
the image above is the result the stimulus used ------------------------------------------------------------------------ - clk <= not clk after 10 ns; process (sclk, ss) begin if (falling_edge(SCLK)) then -- SPI Mode 0 txsrslave <= txsrslave(6 downto 0) & '0'; end if; end process; process (ss) begin if (ss='1') then txsrslave <= rxsrslave; -- x"80000001" after 3 ns; end if; end process; MISO <= txsrslave(7) after 3 ns; process (sclk, mosi) begin if (rising_edge(SCLK)) then -- SPI Mode 0 rxsrslave <= rxsrslave(6 downto 0) & MOSI; end if; end process; tb :PROCESS BEGIN TX_Data <= "00010101"; wait for 3 ns; TX_Start <= '1'; wait until TX_Done='1'; TX_Start <= '0'; wait for 100 ns; TX_Data <= "00001111"; wait for 3 ns; TX_Start <= '1'; wait until TX_Done='1'; TX_Start <= '0'; wait for 100 ns; TX_Data <= "00001111"; wait for 3 ns; TX_Start <= '1'; wait until TX_Done='1'; TX_Start <= '0'; wait; end process;
> Untitled1.jpg 30 KB
I cannot recognize anything on that picture. Can you post a better
readable screenshot?
(preferred as *.gif or *.png, because *.jpg is ok for fotos, but due to
compression losses and artefacts its no good format for such
screenshots)
> you can enlarge the picture by clicking an zooming with the mouse.
Klugscheißer.
Did you do so? And did you recognize anything on that picture then?
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