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Forum: FPGA, VHDL & Verilog Help with VHDL code


Author: Eddie Pena (bertswoot)
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I am new to VHDL so I am still very "green".. here is some code for a 
4bit 8function simple ALU but first the operations:

F2  F1  F0  Output Function    S0 – S4
0  0  0  Output = A Input       S = A
0  0  1  Output = A Complement  S = NOT A
0  1  0  Output = A Plus B      S = A + B
0  1  1  Output = A Minus B     S = A – B
1  0  0  Output = B Input       S = B
1  0  1  Output = B Complement  S = NOT B
1  1  0  Output = Increment A   S = A + 1
1  1  1  Output = Decrement A   S = A – 1

and since its in INTEGER TYPE im cannot use NOT A or NOT B. My code 
compiles fine but since im mew to this how do I get it to work when I 
tranfer it to my eSOC board?

 The code:

ENTITY ALU IS
PORT(
  AI      : IN INTEGER RANGE 0 to 15;
  BI      : IN INTEGER RANGE 0 to 15;
  FO      : IN INTEGER RANGE 0 to 7;
  SOUT             : OUT INTEGER RANGE 0 to 31);
END ALU;

ARCHITECTURE FUNCTION8 OF ALU IS
BEGIN
PROCESS (AI,BI,FO)
BEGIN

  IF FO = 000 THEN
    SOUT <= AI;
  ELSIF FO = 001 THEN
    SOUT <=  -AI;
  ELSIF FO = 010 THEN
    SOUT <= AI + BI;
  ELSIF FO = 011 THEN
    SOUT <= AI - BI;
  ELSIF FO = 100 THEN
    SOUT <= BI;
  ELSIF FO = 101 THEN
    SOUT <=  -BI;
  ELSIF FO = 110 THEN
    SOUT <= AI + 1;
  ELSIF FO = 111 THEN
    SOUT <= AI - 1;

END IF;
END PROCESS;
END FUNCTION8;

I guess what Im really asking is do you see anything wrong with the 
code?? where did I go wrong?? Any suggestions on some reading material 
that will help me better undertsand VHDL would be greatly appreciated..

Author: lkmiller (Guest)
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Did you already do the most easy "hello world!" of hardware: a blinking 
led?
That's the point where I start every new platform (CPLD, FPGA, uC). 
And after seeing the blinking light I know at least how to handle the IO 
pins.

Did you already try to simulate your design?
There's at least one major bug in it: FO has a range to 7, so 010 is out 
of range, because 010 is ten. And 011 is eleven...

Author: Eddie Pena (bertswoot)
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Thanks for the info. I have sucessfully developed and adder/subtractor.. 
Doesnt the range also determine how many inputs I have.. Like for the 
rules above I used 2^3 to get the number of possible combinations which 
is 8.. should I add F0,F1,F2 to the entity as F0 : in integer range 0 to 
1;
F1  : in integer range 0 to 1; and so on.. or am I completely off??

Author: Schlumpf (Guest)
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In this case I would use std_logic_vector for F0 to F2 and I would 
choose another name than FO for it. Because the risk of confusion about 
O or 0 is very high.

e.g.
F      : IN std_logic_vector(2 downto 0);
...
  IF F = "000" THEN
    SOUT <= AI;

F is an array of bits and not "number" any more..

Author: Schlumpf (Guest)
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But if you like to keep integer for F
you have to write:
  IF FO = 0 THEN
    SOUT <= AI;
  ELSIF FO = 1 THEN
    SOUT <=  -AI;
  ELSIF FO = 2 THEN
    SOUT <= AI + BI;
  ELSIF FO = 3 THEN
    SOUT <= AI - BI;
  ELSIF FO = 4 THEN
    SOUT <= BI;
  ELSIF FO = 5 THEN
    SOUT <=  -BI;
  ELSIF FO = 6 THEN
    SOUT <= AI + 1;
  ELSIF FO = 7 THEN
    SOUT <= AI - 1;

Author: Eddie Pena (bertswoot)
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You are just freaking awesome!!!!!! thank you so much I went ahead and 
used std_logic_vector and it works like a charm.. well everything but 
the NOT A and NOT B part which I had as -A and -B for some reason. But 
the rest of it worked great.. I cant thank you enough!!!!

Author: Eddie Pena (bertswoot)
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never mind it all works great.. you guys are awesome!! thank you for 
your time I really do apreciate it!

Author: Schlumpf (Guest)
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Well, of course it must be "NOT" instead of "-"... :-)
My fault. I just saw the problem with the F-vector and didn´t care about 
the rest :-)
But nice to hear that everything works fine now..

An additional hint:
If you go on coding in VHDL try to think in "Hardware" like "wires", 
"registers", "multiplexers",... and try do describe this in VHDL. It´s 
not "software" that runs command by command on the target device. VHLD 
describes the function and interconnetction of hardware-elements in the 
device.
If you try to think this way whilst coding, you will get good synthesis 
results and manage the coming obstacles you surely will be faced to if 
you go on with VHDL.

Author: P. K. (pek)
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Further more, be careful with "IF..ELSIF..ELSIF.." statements. If just 
using "F0" as condition, your synthesizer may come up with a mux as 
desired.
However, if you start including other stuff in the "IF" conditions (e.g. 
FO =3 and ...), you'll end up in very large number of logic levels.

Therefor: Be on the safe side, use "CASE" statements for such a 
situation, which always will end up in a multiplexer.

Author: Eddie Pena (bertswoot)
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Thank you for the info.. I really appreciate all the help..

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