I have a very simple question. I want to prepare a test bench to study a signal, say named X. X is dependent on two signals: one defined in the ENTITY and the other defined in the ARCHITECTURE. How does one properly instantiate the signal coming from the ARCHITECTURE in the test bench code? Is there a trick to do this?
with standard VHDL just have a look at 'translate off' and 'on', e.g. http://quartushelp.altera.com/11.1/mergedProjects/hdl/vhdl/vhdl_file_dir_translate.htm With this statements you can transport signals into a higher level only for simulation. Synthesis will ignore this signals...
I tried the suggestion but was not successful. My aim is to access the signal int_dac_cs in the ENTITY level. I am writing a testbench to test XYZ(0), whose dependencies are (1) int_dac_cs(0) from the ARCHITECTURE and (2) DEF(0) from the ENTITY. Doing --synthesis translate_off/on int_dac_cs in the ARCHITECTURE and assigning it as a port in the ENTITY (so that it becomes accessible in the testbench file produces the following: Error : (vcom-1294) Declaration with designator "int_dac_cs" already exists in this region What is the better way to do this for simulation purposes. Many thanks
1 | ENTITY MCB_base IS |
2 | |
3 | PORT
|
4 | (
|
5 | ABC : IN STD_LOGIC_VECTOR (2 downto 0); |
6 | DEF : IN STD_LOGIC_VECTOR (2 downto 0); |
7 | int_dac_cs :IN STD_LOGIC_VECTOR (2 downto 0); |
8 | |
9 | XYZ : OUT STD_LOGIC_VECTOR (2 downto 0) |
10 | )
|
11 | |
12 | END MCB_base; |
13 | |
14 | |
15 | |
16 | ARCHITECTURE mcb1 OF MCB_base IS |
17 | |
18 | --synthesis translate_off
|
19 | SIGNAL int_dac_cs : STD_LOGIC_VECTOR (DAC_NUM-1 downto 0); |
20 | --synthesis translate_on
|
21 | |
22 | --then blah blah blah
|
23 | |
24 | |
25 | --signal behavior here
|
26 | XYZ(0) <= ABC(0) when int_dac_cs(0) and DEF(0); |
27 | END mcb1; |
Try:
1 | ENTITY MCB_base IS |
2 | |
3 | PORT
|
4 | (
|
5 | ABC : IN STD_LOGIC_VECTOR (2 downto 0); |
6 | DEF : IN STD_LOGIC_VECTOR (2 downto 0); |
7 | XYZ : OUT STD_LOGIC_VECTOR (2 downto 0); |
8 | dac_cs : OUT STD_LOGIC_VECTOR (2 downto 0) |
9 | )
|
10 | |
11 | END ENTITY MCB_base; |
12 | |
13 | |
14 | |
15 | ARCHITECTURE mcb1 OF MCB_base IS |
16 | |
17 | SIGNAL int_dac_cs : STD_LOGIC_VECTOR (DAC_NUM-1 downto 0); |
18 | |
19 | begin
|
20 | --then blah blah blah
|
21 | |
22 | |
23 | --signal behavior here
|
24 | XYZ(0) <= ABC(0) when int_dac_cs(0) and DEF(0); |
25 | |
26 | dac_cs <= int_dac_cs; |
27 | |
28 | END ARCHITECTURE mcb1; |
Duke
Thanks Duke. However say, I would like to properly instantiate int_dac_cs that belongs to a lpm_shiftreg (altera notations) ie, inside another port map residing in the architecture. So in summary, I want to study the behavior of XYZ from signals defined in the entity and architecture How does one properly define the ports found in the ARCHITECTURE so that they also become ports of the ENTITY. The aim is for the test bench file be able to access them. Thanks!
1 | ENTITY MCB_base IS |
2 | |
3 | PORT
|
4 | (
|
5 | ABC : IN STD_LOGIC_VECTOR (2 downto 0); |
6 | DEF : IN STD_LOGIC_VECTOR (2 downto 0); |
7 | --int_dac_cs :IN STD_LOGIC_VECTOR (2 downto 0);
|
8 | |
9 | XYZ : OUT STD_LOGIC_VECTOR (2 downto 0) |
10 | )
|
11 | |
12 | END MCB_base; |
13 | |
14 | |
15 | |
16 | ARCHITECTURE mcb1 OF MCB_base IS |
17 | |
18 | SIGNAL int_dac_cs : STD_LOGIC_VECTOR (DAC_NUM-1 downto 0); |
19 | |
20 | |
21 | --then blah blah blah
|
22 | clock <= control(STSELCLK) and control(MCBSELECT); --dont worry about this |
23 | |
24 | dacsel_shiftreg : |
25 | lpm_shiftreg
|
26 | GENERIC MAP |
27 | (
|
28 | LPM_WIDTH => DAC_NUM, |
29 | LPM_AVALUE => "001" |
30 | )
|
31 | PORT MAP |
32 | (
|
33 | q=> int_dac_cs, |
34 | clock=> clock, |
35 | shiftin => '0', |
36 | aset => dac_reset |
37 | );
|
38 | |
39 | --signal behaviors here
|
40 | XYZ(0) <= ABC(0) when int_dac_cs(0) and DEF(0); |
41 | XYZ(1) <= ABC(1) when int_dac_cs(1) and DEF(1); |
42 | XYZ(2) <= ABC(2) when int_dac_cs(2) and DEF(2); |
43 | |
44 | END mcb1; |
> How does one properly define the ports found in the ARCHITECTURE so that > they also become ports of the ENTITY. The aim is for the test bench file > be able to access them. Thanks! You can define signals only at one place: entity or architecture. But signals defined in entity have a direction. If the direction is out then the signal can't be readed. There is a construct with an additional internal signal. Maybe you try this (if the direction of int_dac_cs is really in):
1 | ENTITY MCB_base IS |
2 | |
3 | PORT
|
4 | (
|
5 | ABC : IN STD_LOGIC_VECTOR (2 downto 0); |
6 | DEF : IN STD_LOGIC_VECTOR (2 downto 0); |
7 | int_dac_cs :IN STD_LOGIC_VECTOR (2 downto 0); |
8 | |
9 | XYZ : OUT STD_LOGIC_VECTOR (2 downto 0) |
10 | )
|
11 | |
12 | END MCB_base; |
13 | |
14 | |
15 | |
16 | ARCHITECTURE mcb1 OF MCB_base IS |
17 | |
18 | --SIGNAL int_dac_cs : STD_LOGIC_VECTOR (DAC_NUM-1 downto 0);
|
19 | |
20 | |
21 | --then blah blah blah
|
22 | clock <= control(STSELCLK) and control(MCBSELECT); --dont worry about this |
23 | |
24 | dacsel_shiftreg : |
25 | lpm_shiftreg
|
26 | GENERIC MAP |
27 | (
|
28 | LPM_WIDTH => DAC_NUM, |
29 | LPM_AVALUE => "001" |
30 | )
|
31 | PORT MAP |
32 | (
|
33 | q=> int_dac_cs, |
34 | clock=> clock, |
35 | shiftin => '0', |
36 | aset => dac_reset |
37 | );
|
38 | |
39 | --signal behaviors here
|
40 | XYZ(0) <= ABC(0) when int_dac_cs(0) and DEF(0); |
41 | XYZ(1) <= ABC(1) when int_dac_cs(1) and DEF(1); |
42 | XYZ(2) <= ABC(2) when int_dac_cs(2) and DEF(2); |
43 | |
44 | END mcb1; |
Duke
try something like this:
1 | entity top is |
2 | port ( |
3 | -- translate_off
|
4 | tb_x : out std_logic; |
5 | -- translate_on
|
6 | x_in : in std_logic; |
7 | ...
|
8 | );
|
9 | end; |
10 | architecture rtl of top is |
11 | signal x_intern : std_logic; |
12 | signal x_any : std_logic; -- Your internally calculated signal |
13 | begin
|
14 | x_intern <= x_in and x_any; -- The signal to observe |
15 | -- translate_off
|
16 | tx_x <= x_intern; |
17 | -- translate_on
|
18 | end; |
Now you can instatiate this entity as component in your TB (there you don't need the 'translate_' stuff since its only for simulation. tb_x will have the same value/behaviour as x_intern in your architecture. And synthesis will ignore tb_x
Thanks berndl! One problem though, I try to instantiate a signal like that of tx_x with a value '0' and '1'.... but the value remains '0'. fclopez
tx_x is a typo, it must be tb_x (simulation-only output port)
if your simulator supports vhdl 2008, have a look at external names.
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