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Forum: FPGA, VHDL & Verilog Instantiating signals from the ARCHITECTURE in the test bench


Author: FC LOPEZ (Company: x1) (fclopez)
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I have a very simple question. I want to prepare a test bench to study a 
signal, say named X.
X is dependent on two signals: one defined in the ENTITY and the other 
defined in the ARCHITECTURE.

How does one properly instantiate the signal coming from the 
ARCHITECTURE in the test bench code? Is there a trick to do this?

Author: berndl (Guest)
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with standard VHDL just have a look at 'translate off' and 'on', e.g.
http://quartushelp.altera.com/11.1/mergedProjects/...

With this statements you can transport signals into a higher level only 
for simulation. Synthesis will ignore this signals...

Author: FC LOPEZ (Company: x1) (fclopez)
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I tried the suggestion but was not successful. My aim is to access the 
signal int_dac_cs in the ENTITY level. I am writing a testbench to test 
XYZ(0), whose dependencies are (1) int_dac_cs(0) from the ARCHITECTURE 
and (2) DEF(0) from the ENTITY.
Doing --synthesis translate_off/on int_dac_cs in the ARCHITECTURE and 
assigning it as a port in the  ENTITY (so that it becomes accessible in 
the testbench  file produces the following:
Error :  (vcom-1294) Declaration with designator "int_dac_cs" already 
exists in this region

What is the better way to do this for simulation purposes. Many thanks

ENTITY MCB_base IS

 PORT
    (    
     ABC : IN STD_LOGIC_VECTOR (2 downto 0);
     DEF : IN STD_LOGIC_VECTOR (2 downto 0);
     int_dac_cs :IN STD_LOGIC_VECTOR (2 downto 0);
     
     XYZ : OUT STD_LOGIC_VECTOR (2 downto 0)
    )

END MCB_base;



ARCHITECTURE mcb1 OF MCB_base IS

--synthesis translate_off
SIGNAL int_dac_cs : STD_LOGIC_VECTOR (DAC_NUM-1 downto 0); 
--synthesis translate_on

--then blah blah blah 


--signal behavior here
XYZ(0) <= ABC(0)  when int_dac_cs(0) and  DEF(0);
END mcb1;



Author: Duke Scarring (Guest)
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Try:
ENTITY MCB_base IS

 PORT
    (    
     ABC    : IN  STD_LOGIC_VECTOR (2 downto 0);
     DEF    : IN  STD_LOGIC_VECTOR (2 downto 0);
     XYZ    : OUT STD_LOGIC_VECTOR (2 downto 0);
     dac_cs : OUT STD_LOGIC_VECTOR (2 downto 0)
    )

END ENTITY MCB_base;



ARCHITECTURE mcb1 OF MCB_base IS

    SIGNAL int_dac_cs : STD_LOGIC_VECTOR (DAC_NUM-1 downto 0); 

begin
    --then blah blah blah 


    --signal behavior here
    XYZ(0) <= ABC(0)  when int_dac_cs(0) and  DEF(0);

    dac_cs <= int_dac_cs;

END ARCHITECTURE mcb1;

Duke

Author: FC LOPEZ (Company: x1) (fclopez)
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Thanks Duke.
 However say, I would like to properly instantiate  int_dac_cs that 
belongs to a lpm_shiftreg (altera notations) ie, inside another port map 
residing in the architecture. So in summary, I want to study the 
behavior of XYZ from signals defined in the entity and architecture

How does one properly define the ports found in the ARCHITECTURE so that 
they also become ports of the ENTITY. The aim is for the test bench file 
be able to access them. Thanks!



ENTITY MCB_base IS

 PORT
    (    
     ABC : IN STD_LOGIC_VECTOR (2 downto 0);
     DEF : IN STD_LOGIC_VECTOR (2 downto 0);
     --int_dac_cs :IN STD_LOGIC_VECTOR (2 downto 0);
     
     XYZ : OUT STD_LOGIC_VECTOR (2 downto 0)
    )

END MCB_base;



ARCHITECTURE mcb1 OF MCB_base IS

SIGNAL int_dac_cs : STD_LOGIC_VECTOR (DAC_NUM-1 downto 0); 


--then blah blah blah 
clock <= control(STSELCLK) and control(MCBSELECT); --dont worry about this

dacsel_shiftreg  : 
lpm_shiftreg
  GENERIC MAP 
  (
    LPM_WIDTH  => DAC_NUM,
    LPM_AVALUE  => "001"
  )
  PORT MAP 
  (
    q=> int_dac_cs,
    clock=> clock,
    shiftin => '0',
    aset  => dac_reset
  );

--signal behaviors here
XYZ(0) <= ABC(0)  when int_dac_cs(0) and  DEF(0);
XYZ(1) <= ABC(1)  when int_dac_cs(1) and  DEF(1);
XYZ(2) <= ABC(2)  when int_dac_cs(2) and  DEF(2);

END mcb1;




Author: Duke Scarring (Guest)
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> How does one properly define the ports found in the ARCHITECTURE so that
> they also become ports of the ENTITY. The aim is for the test bench file
> be able to access them. Thanks!
You can define signals only at one place: entity or architecture.
But signals defined in entity have a direction. If the direction is 
out then the signal can't be readed. There is a construct with an 
additional internal signal.

Maybe you try this (if the direction of int_dac_cs is really in):
ENTITY MCB_base IS

 PORT
    (    
     ABC : IN STD_LOGIC_VECTOR (2 downto 0);
     DEF : IN STD_LOGIC_VECTOR (2 downto 0);
     int_dac_cs :IN STD_LOGIC_VECTOR (2 downto 0);
     
     XYZ : OUT STD_LOGIC_VECTOR (2 downto 0)
    )

END MCB_base;



ARCHITECTURE mcb1 OF MCB_base IS

--SIGNAL int_dac_cs : STD_LOGIC_VECTOR (DAC_NUM-1 downto 0); 


--then blah blah blah 
clock <= control(STSELCLK) and control(MCBSELECT); --dont worry about this

dacsel_shiftreg  : 
lpm_shiftreg
  GENERIC MAP 
  (
    LPM_WIDTH  => DAC_NUM,
    LPM_AVALUE  => "001"
  )
  PORT MAP 
  (
    q=> int_dac_cs,
    clock=> clock,
    shiftin => '0',
    aset  => dac_reset
  );

--signal behaviors here
XYZ(0) <= ABC(0)  when int_dac_cs(0) and  DEF(0);
XYZ(1) <= ABC(1)  when int_dac_cs(1) and  DEF(1);
XYZ(2) <= ABC(2)  when int_dac_cs(2) and  DEF(2);

END mcb1;

Duke

Author: berndl (Guest)
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try something like this:
entity top is
port (
-- translate_off
  tb_x : out std_logic;
-- translate_on
  x_in : in std_logic;
  ...
);
end;
architecture rtl of top is
  signal x_intern : std_logic;
  signal x_any : std_logic;  -- Your internally calculated signal
begin
  x_intern <= x_in and x_any; -- The signal to observe
-- translate_off
  tx_x <= x_intern;
-- translate_on
end;
Now you can instatiate this entity as component in your TB (there you 
don't need the 'translate_' stuff since its only for simulation. tb_x 
will have the same value/behaviour as x_intern in your architecture. And 
synthesis will ignore tb_x

Author: FC LOPEZ (Company: x1) (fclopez)
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Thanks berndl!
One problem though,

I try to instantiate a signal like that of tx_x with a value '0' and 
'1'.... but the value remains '0'.

fclopez

Author: berndl (Guest)
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tx_x is a typo, it must be tb_x (simulation-only output port)

Author: dasdgw (Guest)
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if your simulator supports vhdl 2008, have a look at external names.

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