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Forum: FPGA, VHDL & Verilog I need help with a VHDL average calculator (sum contains 10 products)


Author: Henk Haring (Company: Fisherman) (theodorush)
Posted on:

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My issue is written in the code (architecture) after the arrow -->
------------------------------------------
------------------------------------------
-- Date        : Sun Jan 13 02:28:08 2013
--
-- Author      : Just me
--
-- Company     : 
--
-- Description : Average reaction time
--
------------------------------------------
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity  Average_reaction_time  is
port(
  clk: in std_logic;
  reset: in std_logic;
  stop: in std_logic;
  reaction_count: in std_logic_vector (15 downto 0);
  reaction_count_average: out std_logic_vector (15 downto 0)
  );
end;

------------------------------------------
------------------------------------------
-- Date        : Sun Jan 13 02:28:08 2013
--
-- Author      : Just me
--
-- Company     : 
--
-- Description : The average of a sum with 10 products
--               The result will be shown on four 7segment display's 
--               with a bcd encoder 
--
------------------------------------------
------------------------------------------
architecture  Behavior  of  Average_reaction_time  is
signal reaction_count0: std_logic_vector (3 downto 0); 
signal reaction_count1: std_logic_vector (3 downto 0);
signal reaction_count2: std_logic_vector (3 downto 0); 
signal reaction_count3: std_logic_vector (3 downto 0); 
signal reaction_count_average0: std_logic_vector (3 downto 0); -
signal reaction_count_average1: std_logic_vector (3 downto 0);
signal reaction_count_average2: std_logic_vector (3 downto 0);
signal reaction_count_average3: std_logic_vector (3 downto 0);
signal count: integer range 0 to 9; 
signal sum0: integer range 0 to 90;
signal sum1: integer range 0 to 90;
signal sum2: integer range 0 to 90;
signal sum3: integer range 0 to 90;
signal product0: integer range 0 to 9;
signal product1: integer range 0 to 9;
signal product2: integer range 0 to 9;
signal product3: integer range 0 to 9;
signal average0: integer range 0 to 9;
signal average1: integer range 0 to 9;
signal average2: integer range 0 to 9;
signal average3: integer range 0 to 9;
begin

--synchronous process
average: process(clk)

begin
--info: assign the current value of input reaction_count to 
--      reactioncount0,1,2,3
reaction_count0 <= reaction_count (3 downto 0);
reaction_count1 <= reaction_count (7 downto 4);
reaction_count2 <= reaction_count (11 downto 8);
reaction_count3 <= reaction_count (15 downto 12);

--info: convert reaction_count0,1,2,3 to integer wich makes deviding by 10     
--      possible
product0 <= conv_integer(reaction_count0);
product1 <= conv_integer(reaction_count1);
product2 <= conv_integer(reaction_count2);
product3 <= conv_integer(reaction_count3);

--info: if reset pressed set every signal to 0
if (reset = '1') then
  reaction_count0 <= "0000";
  reaction_count1 <= "0000";
  reaction_count2 <= "0000";
  reaction_count3 <= "0000";
  reaction_count_average0 <= "0000";
  reaction_count_average1 <= "0000";
  reaction_count_average2 <= "0000";
  reaction_count_average3 <= "0000";
  count <= 0;
  sum0 <= 0;
  sum1 <= 0;
  sum2 <= 0;
  sum3 <= 0;
  product0 <= 0;
  product1 <= 0;
  product2 <= 0;
  product3 <= 0;
  average0 <= 0;
  average1 <= 0;
  average2 <= 0;
  average3 <= 0;
  
  elsif (clk'event and clk = '1') then

--> This is where the issue is: when stop = 1 it keeps adding the product 
--  to the sum until stop = 0. I want it to only add one product to the 
--  specific sum when stop = 1. I have tried stop = 0 and stop'event but 
--  that is not acceptable after a the clk'event. there might be a simple 
--  solution but I cant seem to find it. I really appreciate your help.

    if (stop = '1') then  
    sum0 <= sum0 + product0;
    sum1 <= sum1 + product1;
    sum2 <= sum2 + product2;
    sum3 <= sum3 + product3;
    count <= count + 1;
    end if;
  
    if (count = 10) then
    average0 <= sum0/10;
    average1 <= sum1/10;
    average2 <= sum2/10;
    average3 <= sum3/10;  
    count <= 0;  
    end if;
  reaction_count_average0 <= conv_std_logic_vector(average0, 4);
  reaction_count_average1 <= conv_std_logic_vector(average1, 4);
  reaction_count_average1 <= conv_std_logic_vector(average2, 4);
  reaction_count_average1 <= conv_std_logic_vector(average3, 4);
end if;
end process;
reaction_count_average (3 downto 0) <= reaction_count_average0; 
reaction_count_average (7 downto 4) <= reaction_count_average1;
reaction_count_average (11 downto 8) <= reaction_count_average2;
reaction_count_average (15 downto 12) <= reaction_count_average3;
end Behavior;

Author: Achim S. (Guest)
Posted on:

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is "stop" an external signal, which may switch without defined timing 
with respect to "clk"? If yes, you will run in trouble, cause sooner or 
later stop will switch just at that unfavourable point in time, where 
different parts of your logic recognize different levels of stop and 
compute nonsense.

>>I want it to only add one product to the
>>--  specific sum when stop = 1.

So what you really want is to add in that clk-cycle, where stop has a 
rising edge. You need an edge detector:

....
signal stop_old:std_logic:='1';

if (clk'event and clk = '1') then

    stop_old <= stop; --remember stop-signal of previous clock-cycle

    if (stop = '1') and (stop_old='0') then 
       sum0 <= sum0 + product0 
.....

Author: Henk Haring (Company: Fisherman) (theodorush)
Posted on:

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The stop button is activated by the user, so it might switch without 
defined timing with respect to the "clk". There might indeed be a 
problem, but i think i can solve that by adding  another input.

But, thanks this solution solved my question and helped me for now.

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