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Forum: FPGA, VHDL & Verilog pwm modulation/demodulation


Author: alper yazır (alperyazir)
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hi everyone. I need help about vhdl code of spartan3e.
i wanna communicate two FBGAs. For example, i am using rotary switch to 
produce pwm(it arranges my duty cycles. and i produce my pwm from my 1st 
FBGA and use it 2nd FBGA. i tried but it didnt happened.
please help me ??

my codes is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rotaryEncoder is
Port ( 
      clk  : in    STD_LOGIC; -- C9
      RotA : in    STD_LOGIC; -- K18 PULLUP
      RotB : in    STD_LOGIC; -- G18 PULLUP
      data : inout STD_LOGIC_VECTOR(7 DOWNTO 0); -- E12
      leds : inout STD_LOGIC_VECTOR(7 DOWNTO 0);
      sout : inout std_logic;
      sin  : in std_logic);
 end rotaryEncoder;

 architecture rotaryEncoder of rotaryEncoder is
 signal sta       : STD_LOGIC_VECTOR(1 downto 0);
 signal prr       : STD_LOGIC_vector(1 downto 0);
 signal rotary_in : STD_LOGIC_vector(1 downto 0);
 signal RotA1     : STD_LOGIC;
 signal RotB1     : STD_LOGIC;
 signal s1        :std_logic;
 signal s2        :std_logic;
 signal s3        :std_logic;
 signal s4        :std_logic;
 signal s5        :std_logic_vector(3 downto 0);
 signal s6        :std_logic;
 signal s7        :std_logic_vector(1 downto 0);
 signal cmp        :std_logic_vector(3 downto 0);
 signal xcount3   : std_logic_vector(7 downto 0);
 signal xcount1   : std_logic_vector(8 downto 0);
 signal reg       :std_logic_vector(7 downto 0);
 
 begin
 rotary_filter: 
 process(clk)    
  begin                   
    if clk'event and clk='1' then  
    rotary_in <= RotA & RotB;      
        case rotary_in is  

          when "00" => RotA1 <= '0';     RotB1 <= RotB1;   
          when "01" => RotA1 <= RotA1;   RotB1 <= '0';      
          when "10" => RotA1 <= RotA1;   RotB1 <= '1';     
          when "11" => RotA1 <= '1';     RotB1 <= RotB1;   
          when others => RotA1 <= RotA1; RotB1 <= RotB1;                
        end case;                    
    end if;                        
 end process rotary_filter;     

 direction:
  process(clk) is begin
      if(rising_edge(clk)) then
        case sta & RotA1 & RotB1 is
    when "0001" => prr <= "01"; sta <="01"; -- 01 turn right
          when "0010" => prr <= "00"; sta <="10"; -- 00 turn left
    when "0111" => prr <= "01"; sta <="11"; -- 10 null
    when "0100" => prr <= "00"; sta <="00";
    when "1000" => prr <= "10"; sta <="00";
    when "1011" => prr <= "10"; sta <="11";
    when "1110" => prr <= "10"; sta <="10";
    when "1101" => prr <= "10"; sta <="01";
    when others => null;
        end case;
          if(prr="00") then
            data<=data+1; prr<="10";
          elsif(prr="01") then
            data<=data-1; prr<="10";
          else
            null;
          end if;
       end if;
   end process;

  TRNS:process(clk) is begin 
    if clk'event and clk='1' then
      
        if(xcount1<="000000000") then
        sout<='1';
        elsif(xcount1="000000001") then
        sout<='1';
        elsif(xcount1="000000010") then
        sout<='0';
        elsif(xcount1="000000011") then
        sout<='0';

        elsif((xcount1<=data)and(xcount1>"000000011")) then
            sout<='1';
        elsif(xcount1<="100000011") then
          sout<='0';
        elsif(xcount1="100000011") then
        xcount1<="000000000";  
        end if;
    xcount1<= xcount1 + 1;
    end if;
 end process;
 
 RCV:process(clk,sin,s1,s2,s3,s4,s5,s6,s7)is begin
       if(rising_edge(clk)) then
        
          s1<=sin;
         s2<=s1;
         s3<=s2;
         s4<=s3;
          s5<=s1&s2&s3&s4;
          s7<=s6&sin;
         if(s5="0011") then
        s6<='1';
        end if;
        if(s7="11") then
        
            leds<=leds;
            reg<=xcount3;
        else
            leds<=reg-3;
        end if;
        xcount3<= xcount3 + 1;
        
        if(xcount3="11111111") then
          xcount3<="00000000";
        end if;
         if(reg="11111111") then
         reg<="00000000";
         end if;
      end if;
    end process;
 end rotaryEncoder;


Author: Lothar Miller (lkmiller) (Moderator)
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Did you simulate your design? How does the testbench look like? And: 
what's the problem at all? What does not "happen"? What do you expect? 
And what do you get?

Author: Manni (Guest)
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I am again surprised, how complex a AB-decoding can be done. I never 
learned about that and therefor was very new to it, when I had to do it 
the first time. What I am doing:

I sample the incoming value with a frequency which is low enough, that 
bouncing has no effect anymore and decide, if the value changed. When it 
inreased or had an overrun, I am adding 1 to my result, in the other 
case i substracted one. Allways worked sufficiently.

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