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Forum: FPGA, VHDL & Verilog Testbench of d flip flop


Author: Fahim Khan (fahimk)
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Hi,

I am trying to run vhdl code of d flip flop on ghdl.

I am not getting any error while compiling and executing,however when I 
try to run it, it doesnt come to prompt again it keeps on runing.
Please let me know where I am making mistake.

My code is as below.
---------------------------------------------

library ieee ;
use ieee.std_logic_1164.all;


---------------------------------------------

entity dff is
port ( din:     in std_logic;
       dclk:     in std_logic;
       qout:    out std_logic;
       nqout:   out std_logic
     );

end dff;
--------------------------------------------

architecture behavioral of dff is

begin
        process(din,dclk)
        begin
          --- clock rising edge
        if(dclk='1' and dclk'event) then
                qout <= din;
                nqout <= not din;
        end if;
        end process;
end behavioral;

------------------------------------------              
------TestBench of D Flip Flop------------                      
------------------------------------------

library ieee;
use ieee.std_logic_1164.all;


entity dff_tb is
end dff_tb;


------------------------------------------

architecture testbench of dff_tb is

        signal T_din:   std_logic;
        signal T_dclk:  std_logic;
        signal T_qout:  std_logic;
        signal T_nqout: std_logic;

        constant clk_period : time := 50 ns;

        component dff
        port ( din:     in std_logic;
               dclk:    in std_logic;
               qout:    out std_logic;
               nqout:   out std_logic
             );
        end component;

begin

    dut_dff: dff port map (T_din,T_dclk,T_qout,T_nqout);

    process
        begin
          T_dclk <= '0';
          wait for clk_period/2;
          T_dclk <= '1';
          wait for clk_period/2;
    end process;

    process

        begin
          --case1
          T_din <= '0';
          wait for clk_period*2;

          --case2
          T_din <= '1';
          wait for clk_period*1.5;

          --case3
          T_din <= '0';
          wait for clk_period*0.5;

          --case4
          T_din <= '1';

        wait;
   end process;

end testbench;

 

Author: P. K. (pek)
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You have to stop the testbench somehow at the end, e.g. by an assertion 
like:
    assert false
      report " ===== Verification run 'TESTBENCH' finished ====="
      severity failure;

Otherwise, your clock process will run forever...

Author: Lothar Miller (lkmiller) (Moderator)
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> it keeps on runing.
Which toolchain do you use?
Usually there's also a button "run for a specified time". There you can 
say: run my simulation for 100ns, then stop.

BTW:
     dut_dff: dff port map (T_din,T_dclk,T_qout,T_nqout);
Don't use positional assignment. I promise you: you will run into 
problems with this after the first minor change. Where's the problem 
here:
     dut_dff: dff port map (T_din,T_dclk,T_nqout,T_qout);
Write it with explicit assignments, and then you can twist and move 
every port:
dut_dff: dff port map (qout=>T_qout,din=>T_din,dclk=>T_dclk,nqout=>T_nqout);

Author: Fahim Khan (fahimk)
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Hi,

I changed the code to use assert statement but still getting same issue.
---------------------------------------------

library ieee ;
use ieee.std_logic_1164.all;


---------------------------------------------

entity dff is
port ( din:  in std_logic;
       dclk:     in std_logic;
       qout:    out std_logic;
       nqout:   out std_logic
     );

end dff;


--------------------------------------------

architecture behavioral of dff is

begin
  process(din,dclk)
  begin
    --- clock rising edge
  if(dclk='1' and dclk'event) then
    qout <= din;
    nqout <= not din;
  end if;
  end process;
end behavioral;

------------------------------------------    

------TestBench of D Flip Flop------------      
------------------------------------------

library ieee;
use ieee.std_logic_1164.all;


entity dff_tb is
end dff_tb;


------------------------------------------

architecture testbench of dff_tb is
 
  signal T_din:  std_logic;
  signal T_dclk:  std_logic;
  signal T_qout:  std_logic;
  signal T_nqout: std_logic;
  
  component dff 
  port ( din:   in std_logic;
         dclk:  in std_logic;
         qout:    out std_logic;
         nqout:  out std_logic
       );
  end component;

begin
           
    dut_dff: dff port map (T_din,T_dclk,T_qout,T_nqout);

    process
  begin
    T_dclk <= '0';
    wait for 5 ns;
    T_dclk <= '1';
    wait for 5 ns;
    end process;

    process 
  
  variable err_cnt: integer := 0; 

  begin
    --case1
   T_din <= '1';
  wait for 12 ns;     
  assert (T_qout='1') report "Error1!" severity error;
  if (T_qout/='1') then
      err_cnt := err_cnt + 1;
  end if;

  -- case 2
  T_din <=  '0';   
  wait for 28 ns;
  assert (T_qout='0') report "Error2!" severity error;
  if (T_qout/='0') then
      err_cnt := err_cnt + 1;
  end if;

  -- case 3
  T_din <= '1';            
  wait for 2 ns;
  assert (T_qout='0') report "Error3!" severity error;
  if (T_qout/='0') then
      err_cnt := err_cnt + 1;
  end if;
    
  -- case 4
  T_din <= '0';
  wait for 10 ns;
  assert (T_qout='0') report "Error4!" severity error;
  if (T_qout/='0') then
      err_cnt := err_cnt + 1;
  end if;

  -- case 5
  T_din <=  '1';    
  wait for 20 ns;    
  assert (T_qout='1') report "Error5!" severity error;   
  if (T_qout/='0') then
      err_cnt := err_cnt + 1;
  end if;
   
  -- summary of all the tests
  if (err_cnt=0) then       
      assert false 
      report "Testbench of Adder completed successfully!" 
      severity note; 
  else 
      assert true 
      report "Something wrong, try again" 
      severity error; 
  end if; 
  
  wait;
   end process;
   
end testbench;

Author: Fahim Khan (fahimk)
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Hi,

I am using ghdl.

Author: Fahim Khan (fahimk)
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Got it I am stoping it after 500ns using

ghdl -r dff_tb --stop-time=500ns

Author: P. K. (pek)
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Fahim Khan wrote:
>   if (err_cnt=0) then
>       assert false
>       report "Testbench of Adder completed successfully!"
>       severity note;
>   else
>       assert true
>       report "Something wrong, try again"
>       severity error;
>   end if;

Wrong, needs to be:
   if (err_cnt=0) then
       assert false
       report "Testbench of Adder completed successfully!"
       severity failure;
   else
       assert false
       report "Something wrong, try again"
       severity failure;
   end if;

The assert condition has always to be "false", if you want it to trig...
...then it will work as expected. And to be sure it stops, use severity 
"failure", this is usually a break condition by default.

Author: berndl (Guest)
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With GHDL and other simulators (e.g. ModelSim) I usually have in my TB:
   clk_process : process
   begin
    wait for clk_period*5;
    loop
      clk50 <= '1';
      wait for clk_period/2;
      clk50 <= '0';
      wait for clk_period/2;
      exit when end_of_sim = '1';
    end loop;
    wait;
   end process;
...this (or something similar) for all special processes I have in the 
TB...

And in my 'main' TB execution process (snippet of the end of this 
process):
    --assert end_of_sim = '1'
    --  report "---- End of module simulation reached ----" severity note;
    end_of_sim <= '1';
    wait;
   end process;

This will stop GHDL and others, either with the 'assert' (commented out 
here) or 'automagically'... (of course, 'end_of_sim' 
initially/previously set to '0')

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