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Forum: FPGA, VHDL & Verilog Acquiring data from files


von eduardo m. (edumelara)


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I am trying to multiply a series of values that I am getting from txt 
files.
My ideia is to get the data from 1 file, multiply for every data from 
the second file, get the second valor from the first file and again 
multiply it with all the values in the second file and so on.
Can anyone give me a light?
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    estimulo: process
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    variable linha   : LINE;
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    variable valor1, valor2  : std_logic_vector(tamanho-1 downto 0);
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    variable decisao : boolean;
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    begin
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     file_open(constante, "C:/Users/Eduardo/Desktop/Pos/VHDL/projfinal/proj7/vhdl/constante.txt", read_mode);
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     file_open(variavelx, "C:/Users/Eduardo/Desktop/Pos/VHDL/projfinal/proj7/vhdl/variavelx.txt", read_mode);
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     wait until (rst = '0');
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     report "fim do reset";
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       while not endfile(variavelx) loop
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        readline(variavelx, linha);
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        read (linha, valor2);
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        b_i <= (unsigned(valor2(tamanho-1 downto 0)));
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         while not endfile(constante) loop
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          readline(constante, linha);
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          read (linha, valor1);
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          a_i <= (unsigned(valor1(tamanho-1 downto 0)));  
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          read (linha, decisao);
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          caso <= decisao;  
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          report "subindo valores";
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          wait for 3*clk_period;
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         end loop;

von kaz (Guest)


Attached files:

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Hi,
maybe the attached example will help you a bit.

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