Forum: FPGA, VHDL & Verilog Acquiring data from files

Author: eduardo melara (edumelara)
Posted on:

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I am trying to multiply a series of values that I am getting from txt 
My ideia is to get the data from 1 file, multiply for every data from 
the second file, get the second valor from the first file and again 
multiply it with all the values in the second file and so on.
Can anyone give me a light?
    estimulo: process
    variable linha   : LINE;
    variable valor1, valor2  : std_logic_vector(tamanho-1 downto 0);
    variable decisao : boolean;
     file_open(constante, "C:/Users/Eduardo/Desktop/Pos/VHDL/projfinal/proj7/vhdl/constante.txt", read_mode);
     file_open(variavelx, "C:/Users/Eduardo/Desktop/Pos/VHDL/projfinal/proj7/vhdl/variavelx.txt", read_mode);
     wait until (rst = '0');
     report "fim do reset";
       while not endfile(variavelx) loop
        readline(variavelx, linha);
        read (linha, valor2);
        b_i <= (unsigned(valor2(tamanho-1 downto 0)));
         while not endfile(constante) loop
          readline(constante, linha);
          read (linha, valor1);
          a_i <= (unsigned(valor1(tamanho-1 downto 0)));  
          read (linha, decisao);
          caso <= decisao;  
          report "subindo valores";
          wait for 3*clk_period;
         end loop;

Author: kaz (Guest)
Posted on:
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maybe the attached example will help you a bit.


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