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Forum: FPGA, VHDL & Verilog Generic component inside generic component


Author: Eduardo (Guest)
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Hello.

I am designing a vhdl code that has a generic size setting a bunch of 
operations.
I cannot synthetize it with quartus (Error (10346): VHDL error at 
mac.vhd(7): formal port or parameter "width" must have actual or default 
value), but I am able to compile with modelsim.

My question is, can I put a generic component inside another? If dont, 
how should I proceed?
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

ENTITY main IS
  generic (
    size : integer := 4);
  port (
    clk     : in  std_logic;
    rst     : in  std_logic;
    a_i     : in  std_logic_vector(size-1 downto 0);
    b_i     : in  std_logic_vector(size-1 downto 0);
    out_o    : out std_logic_vector(2*size-1 downto 0)
    );
END main;


ARCHITECTURE bhv OF main IS
  COMPONENT mac
  generic (
    width : integer);
  port (
    clk     : in  std_logic;
    rst     : in  std_logic;
    a_i     : in  std_logic_vector(width-1 downto 0);
    b_i     : in  std_logic_vector(width-1 downto 0);
    acc   : in  std_logic_vector(2*width-1 downto 0);
    out_o    : out std_logic_vector(2*width-1 downto 0)
    );
   END COMPONENT;

  signal acc  : std_logic_vector(2*size-1 downto 0) := (others => '0');
  
  
BEGIN

      mac1: mac GENERIC MAP (size) PORT MAP (clk, rst, a_i, b_i, acc, out_o);

  END bhv; 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

ENTITY mac IS
  generic (
    width : integer);
  port (
    clk     : in  std_logic;
    rst     : in  std_logic;
    a_i     : in  std_logic_vector(width-1 downto 0);
    b_i     : in  std_logic_vector(width-1 downto 0);
    acc   : in  std_logic_vector(2*width-1 downto 0);
    out_o    : out std_logic_vector(2*width-1 downto 0)
    );
END mac;


ARCHITECTURE bhv OF mac IS
  COMPONENT mul
   generic (
      W_g     : integer);
    port (
      clk      : in  std_logic;
      rst      : in  std_logic;
      a_i      : in  std_logic_vector(W_g-1 downto 0);
      b_i     : in  std_logic_vector(W_g-1 downto 0);
      outm_o   : out std_logic_vector(2*W_g-1 downto 0)
    );
   END COMPONENT;

  COMPONENT soma
   generic (
      W_gs : integer);
    port (
      clk      : in  std_logic;
      rst      : in  std_logic;
      outm_o   : in  std_logic_vector(2*W_gs-1 downto 0);
      acc     : in  std_logic_vector(2*W_gs-1 downto 0);
      outs_o   : out std_logic_vector(2*W_gs-1 downto 0)
    );
   END COMPONENT;   
        
  signal outm_o, outs_o   : std_logic_vector (2*width-1 downto 0) := (OTHERS => '0');

  
BEGIN
      mul1: mul GENERIC MAP (width) PORT MAP (clk, rst, a_i, b_i, outm_o);
      soma1: soma GENERIC MAP (width) PORT MAP (clk, rst, outm_o, acc, outs_o);
    out_o <= outs_o;
  END bhv; 

Author: Klaus (Guest)
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> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
> use ieee.numeric_std.all;

1) Only use libraries you really need! In your case this is only the 
first one

2) Don't use ieee.std_logic_arith and ieee.std_logic_unsigned at all

3) Don't use positional assignments. Use the named assignment! Makes you 
code much more readable.

4) Show us to which line your error message exactly belongs!

Author: Eduardo (Guest)
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Un, ok.

What do you mean by "3) Don't use positional assignments. Use the named 
assignment! Makes you code much more readable."


Quartus points to this generic value:
ENTITY mac IS
  generic (
    width : integer);
  port (
    clk     : in  std_logic;
    rst     : in  std_logic;
    a_i     : in  std_logic_vector(width-1 downto 0);
    b_i     : in  std_logic_vector(width-1 downto 0);
    acc   : in  std_logic_vector(2*width-1 downto 0);
    out_o    : out std_logic_vector(2*width-1 downto 0)
    );
END mac;

Author: Klaus (Guest)
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> What do you mean by "3) Don't use positional assignments. Use the named
> assignment! Makes you code much more readable."

I mean the following syntax:
      mac1: mac 
            GENERIC MAP (width => size) 
            PORT MAP (clk => clk,
                      rst => rst,
                      a_i => a_i,
                      b_i => b_i,
                      acc => acc,
                      out_o => out_o);
So the order of assignments in the generic and port map is unimportant, 
because it is described explicit, which signal is connected to which 
port. But that's not the origin of your error message. Just a general 
advice ;-)


> 1) Only use libraries you really need! In your case this is only the
> first one

I'm sorry. I did't see the integer generic. So you need 
ieee.std_logic_1164 and ieee.numeric_std

Regarding your error message: In general it is no problem, to use a 
generic value like this. Maybe Quartus has a problem with generics on 
top level entities? This is just a guess. Because the code look ok for 
me.

Author: Eduardo (Guest)
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Thanks for the advice.

I am out of ideas to fix this =[

Author: Eduardo (Guest)
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Got it!!!

Just had to set main vhdl file as top level entity!

But thanks for those hints =D

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